| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SMEInstrFormats.td | 2445 // SME2 Dot Products and MLA
2768 // SME2 multi-vec indexed long long MLA one source 16-bit
2795 // SME2 multi-vec indexed long long MLA one source 32-bit
2828 // SME2 multi-vec indexed long long MLA one source 64-bit
2889 //SME2 multi-vec indexed long long MLA two sources 32-bit
2905 // SME2 multi-vec indexed long long MLA four sources 32-bit
2947 // SME2 multi-vec indexed long long MLA two sources 64-bit
2963 // SME2 multi-vec indexed long long MLA four sources 64-bit
3047 //SME2 single-multi long long MLA two and four sources
3081 // SME2 multiple vectors long long MLA two sources
[all …]
|
| H A D | AArch64SchedOryon.td | 1487 "^(S|U|SQ)(MLA|MSL|MUL)(L|L2)v")>;
1521 "^SQRD(MLA|MLS|MUL)Hv")>;
|
| H A D | AArch64SchedCyclone.td | 529 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
|
| H A D | AArch64SchedKryoDetails.td | 1606 (instregex "(MLA|MLS|MUL)(v8i8|v4i16|v2i32)(_indexed)?")>;
1612 (instregex "(MLA|MLS|MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?")>;
|
| H A D | AArch64SchedA64FX.td | 2086 (instregex "^FABD_Z", "^F(ADD|SUBR?)_.*Z_", "^FN?(MAD|MLA|MLS|MSB)_ZP",
2117 def : InstRW<[A64FXWrite_FMAIndexed], (instregex "^F(MLA|MLS|MUL)_ZZZI")>;
|
| H A D | AArch64TargetTransformInfo.cpp | 1581 if (auto MLA = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul, in instCombineSVEVectorAdd() local
1584 return MLA; in instCombineSVEVectorAdd()
|
| H A D | AArch64SchedNeoverseV1.td | 1505 "^(MLA|MLS|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;
|
| H A D | AArch64InstrInfo.td | 5546 // MLA and MLS are generated in MachineCombine
5547 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>;
7807 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", null_frag>;
|
| H A D | SVEInstrFormats.td | 3299 //class for generating pseudo for SVE MLA/MAD/MLS/MSB
|
| H A D | AArch64InstrFormats.td | 11301 // ARMv8.3 Complex ADD/MLA instructions
|
| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFeatures.td | 308 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
312 "Expand VFP/NEON MLA/MLS instructions">;
|
| H A D | ARMScheduleSwift.td | 246 (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
|
| H A D | ARMScheduleR52.td | 271 (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
|
| H A D | ARMScheduleA57.td | 267 // Multiply accumulate: MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB,
|
| H A D | ARMScheduleA9.td | 2548 (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS",
|
| H A D | ARMInstrInfo.td | 4347 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
4362 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
6444 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
|
| /src/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 769 def MLA : IOpInst<"vmla", "....", "dQd", OP_MLA>;
786 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
|
| /src/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 2578 // SVE2 MLA LANE.
2598 // SVE2 MLA Unpredicated.
|
| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 17491 SDValue MLA; in visitFREM() local
17493 MLA = DAG.getNode(ISD::FMA, DL, VT, DAG.getNode(ISD::FNEG, DL, VT, Rnd), in visitFREM()
17497 MLA = DAG.getNode(ISD::FSUB, DL, VT, N0, Mul); in visitFREM()
17499 return NeedsCopySign ? DAG.getNode(ISD::FCOPYSIGN, DL, VT, MLA, N0) : MLA; in visitFREM()
|