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Searched refs:MI (Results 1 – 25 of 1153) sorted by relevance

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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h52 MachineInstr *MI; member
172 bool tryCombineCopy(MachineInstr &MI);
173 bool matchCombineCopy(MachineInstr &MI);
174 void applyCombineCopy(MachineInstr &MI);
190 bool tryCombineExtendingLoads(MachineInstr &MI);
191 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
192 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
195 bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo);
199 bool matchCombineExtractedVectorLoad(MachineInstr &MI, BuildFnTy &MatchInfo);
201 bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
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H A DLegalizerHelper.h94 LegalizeResult legalizeInstrStep(MachineInstr &MI,
98 LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver);
102 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
107 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
110 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
114 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
118 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
123 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
137 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
143 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
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/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp39 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
40 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
41 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
42 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
43 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
44 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
45 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
68 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
69 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
70 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
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/src/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.h34 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
38 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
41 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
42 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
45 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
48 void printOperand(const MCInst *MI, unsigned opNum, raw_ostream &O);
49 void printImmediate(const MCInst *MI, unsigned opNum, raw_ostream &O);
51 void printMoveMask(const MCInst *MI, unsigned opNum, raw_ostream &O);
53 void printMoveMaskR(const MCInst *MI, unsigned opNum, raw_ostream &O);
54 void printDisp(const MCInst *MI, unsigned opNum, raw_ostream &O);
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/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h57 Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
221 MachineBasicBlock::iterator MI) const override;
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) const override;
231 bool PredicateInstruction(MachineInstr &MI,
242 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
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/src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp239 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, in getRegOperandNumElts() argument
241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
250 static void printMasking(raw_ostream &OS, const MCInst *MI, in printMasking() argument
252 const MCInstrDesc &Desc = MCII.get(MI->getOpcode()); in printMasking()
264 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
274 static bool printFMAComments(const MCInst *MI, raw_ostream &OS, in printFMAComments() argument
277 unsigned NumOperands = MI->getNumOperands(); in printFMAComments()
296 switch (MI->getOpcode()) { in printFMAComments()
302 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
306 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
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H A DX86IntelInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
40 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
41 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
45 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
46 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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H A DX86ATTInstPrinter.h27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
33 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
39 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
40 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
43 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
44 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
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/src/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp39 void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
42 if (!printAliasInstr(MI, Address, STI, OS)) in printInst()
43 printInstruction(MI, Address, STI, OS); in printInst()
47 void VEInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand() argument
49 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
67 void VEInstPrinter::printMemASXOperand(const MCInst *MI, int OpNum, in printMemASXOperand() argument
72 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
74 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand()
78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
79 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
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/src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
34 void printInstruction(const MCInst *MI, uint64_t Address,
36 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
38 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
45 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
47 void printOperand(const MCInst *MI, uint64_t Address, unsigned OpNum,
50 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
52 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
55 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
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H A DARMInstPrinter.cpp88 void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
91 unsigned Opcode = MI->getOpcode(); in printInst()
95 const MCOperand &Reg = MI->getOperand(0); in printInst()
103 const MCOperand &Reg = MI->getOperand(0); in printInst()
111 const MCOperand &Reg = MI->getOperand(0); in printInst()
119 const MCOperand &Reg = MI->getOperand(0); in printInst()
129 const MCOperand &Dst = MI->getOperand(0); in printInst()
130 const MCOperand &MO1 = MI->getOperand(1); in printInst()
131 const MCOperand &MO2 = MI->getOperand(2); in printInst()
132 const MCOperand &MO3 = MI->getOperand(3); in printInst()
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h58 static inline bool isVCTP(const MachineInstr *MI) { in isVCTP() argument
59 switch (MI->getOpcode()) { in isVCTP()
71 static inline bool isDoLoopStart(const MachineInstr &MI) { in isDoLoopStart() argument
72 return MI.getOpcode() == ARM::t2DoLoopStart || in isDoLoopStart()
73 MI.getOpcode() == ARM::t2DoLoopStartTP; in isDoLoopStart()
76 static inline bool isWhileLoopStart(const MachineInstr &MI) { in isWhileLoopStart() argument
77 return MI.getOpcode() == ARM::t2WhileLoopStart || in isWhileLoopStart()
78 MI.getOpcode() == ARM::t2WhileLoopStartLR || in isWhileLoopStart()
79 MI.getOpcode() == ARM::t2WhileLoopStartTP; in isWhileLoopStart()
82 static inline bool isLoopStart(const MachineInstr &MI) { in isLoopStart() argument
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/src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
34 return MI.getOperand(OpNo).getReg() == R; in isReg()
80 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
83 switch (MI->getOpcode()) { in printInst()
93 printSaveRestore(MI, STI, O); in printInst()
98 printSaveRestore(MI, STI, O); in printInst()
103 printSaveRestore(MI, STI, O); in printInst()
108 printSaveRestore(MI, STI, O); in printInst()
114 if (!printAliasInstr(MI, Address, STI, O) && in printInst()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp76 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction() argument
77 CurrCycleInstr = MI; in EmitInstruction()
123 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) { in isXDL() argument
124 unsigned Opcode = MI.getOpcode(); in isXDL()
126 if (!SIInstrInfo::isMAI(MI) || in isXDL()
139 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS() argument
140 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
143 switch (MI.getOpcode()) { in isSendMsgTraceDataOrGDS()
154 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
155 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS()
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H A DSIMemoryLegalizer.cpp223 void reportUnsupported(const MachineBasicBlock::iterator &MI,
239 constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const;
248 getLoadInfo(const MachineBasicBlock::iterator &MI) const;
253 getStoreInfo(const MachineBasicBlock::iterator &MI) const;
258 getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const;
263 getAtomicCmpxchgOrRmwInfo(const MachineBasicBlock::iterator &MI) const;
284 bool enableNamedBit(const MachineBasicBlock::iterator MI,
295 virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
302 virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
309 virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
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H A DSIInstrInfo.h52 void insert(MachineInstr *MI);
71 bool isDeferred(MachineInstr *MI);
107 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
114 MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
179 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
186 isCopyInstrImpl(const MachineInstr &MI) const override;
188 bool swapSourceModifiers(MachineInstr &MI,
192 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
230 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
234 bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
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H A DAMDGPULegalizerInfo.h37 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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/src/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp70 void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
73 printInstruction(MI, Address, O); in printInst()
81 void XtensaInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand() argument
83 printOperand(MI->getOperand(OpNum), O); in printOperand()
86 void XtensaInstPrinter::printMemOperand(const MCInst *MI, int OpNum, in printMemOperand() argument
88 OS << getRegisterName(MI->getOperand(OpNum).getReg()); in printMemOperand()
90 printOperand(MI, OpNum + 1, OS); in printMemOperand()
93 void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum, in printBranchTarget() argument
95 const MCOperand &MC = MI->getOperand(OpNum); in printBranchTarget()
96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
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/src/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp38 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
42 printOperand(MI, OpNo0, OS); in printInst()
44 printOperand(MI, OpNo1, OS); in printInst()
48 static bool usesGivenOffset(const MCInst *MI, int AddOffset) { in usesGivenOffset() argument
49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
55 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { in isPreIncrementForm() argument
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
57 return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset); in isPreIncrementForm()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h27 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
28 void printInstruction(const MCInst *MI, uint64_t Address,
33 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
39 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
41 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
43 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
48 void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
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/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCBranchFinalize.cpp51 void replaceWithBRcc(MachineInstr *MI) const;
52 void replaceWithCmpBcc(MachineInstr *MI) const;
95 static bool isBRccPseudo(MachineInstr *MI) { in isBRccPseudo() argument
96 return !(MI->getOpcode() != ARC::BRcc_rr_p && in isBRccPseudo()
97 MI->getOpcode() != ARC::BRcc_ru6_p); in isBRccPseudo()
100 static unsigned getBRccForPseudo(MachineInstr *MI) { in getBRccForPseudo() argument
101 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction."); in getBRccForPseudo()
102 if (MI->getOpcode() == ARC::BRcc_rr_p) in getBRccForPseudo()
107 static unsigned getCmpForPseudo(MachineInstr *MI) { in getCmpForPseudo() argument
108 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction."); in getCmpForPseudo()
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h30 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
36 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
37 virtual void printInstruction(const MCInst *MI, uint64_t Address,
39 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
41 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
52 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI,
56 bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
59 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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/src/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp30 unsigned CSKYMCCodeEmitter::getOImmOpValue(const MCInst &MI, unsigned Idx, in getOImmOpValue() argument
33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
39 CSKYMCCodeEmitter::getImmOpValueIDLY(const MCInst &MI, unsigned Idx, in getImmOpValueIDLY() argument
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
50 CSKYMCCodeEmitter::getImmOpValueMSBSize(const MCInst &MI, unsigned Idx, in getImmOpValueMSBSize() argument
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
54 const MCOperand &LSB = MI.getOperand(Idx + 1); in getImmOpValueMSBSize()
68 void CSKYMCCodeEmitter::expandJBTF(const MCInst &MI, SmallVectorImpl<char> &CB, in expandJBTF() argument
77 MCInstBuilder(MI.getOpcode() == CSKY::JBT_E ? CSKY::BF16 : CSKY::BT16) in expandJBTF()
78 .addOperand(MI.getOperand(0)) in expandJBTF()
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp55 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
64 MI->getOperand(2).isExpr()) { in printInst()
65 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) && in printInst()
69 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && in printInst()
74 printOperand(MI, 0, STI, O); in printInst()
76 printOperand(MI, 2, STI, O); in printInst()
78 printOperand(MI, 1, STI, O); in printInst()
86 unsigned LastOp = MI->getNumOperands() - 1; in printInst()
87 if (MI->getNumOperands() > 1) { in printInst()
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/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp28 bool SPIRVInstrInfo::isConstantInstr(const MachineInstr &MI) const { in isConstantInstr()
29 switch (MI.getOpcode()) { in isConstantInstr()
50 bool SPIRVInstrInfo::isInlineAsmDefInstr(const MachineInstr &MI) const { in isInlineAsmDefInstr()
51 switch (MI.getOpcode()) { in isInlineAsmDefInstr()
60 bool SPIRVInstrInfo::isTypeDeclInstr(const MachineInstr &MI) const { in isTypeDeclInstr()
61 auto &MRI = MI.getMF()->getRegInfo(); in isTypeDeclInstr()
62 if (MI.getNumDefs() >= 1 && MI.getOperand(0).isReg()) { in isTypeDeclInstr()
63 auto DefRegClass = MRI.getRegClassOrNull(MI.getOperand(0).getReg()); in isTypeDeclInstr()
66 return MI.getOpcode() == SPIRV::OpTypeForwardPointer; in isTypeDeclInstr()
70 bool SPIRVInstrInfo::isDecorationInstr(const MachineInstr &MI) const { in isDecorationInstr()
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