| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetSchedule.h | 46 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
59 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
102 const MCSchedClassDesc *SC = nullptr) const;
105 const MCSchedClassDesc *SC = nullptr) const;
109 const MCSchedClassDesc *SC = nullptr) const;
133 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
137 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
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| H A D | MachineTraceMetrics.h | 65 struct MCSchedClassDesc;
299 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = std::nullopt,
300 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = std::nullopt) const;
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| H A D | ScheduleDAGInstrs.h | 44 struct MCSchedClassDesc;
272 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
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| H A D | ScheduleDAG.h | 39 struct MCSchedClassDesc;
255 const MCSchedClassDesc *SchedClass =
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| H A D | MachinePipeliner.h | 481 void reserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
483 void unreserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
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| H A D | MachineScheduler.h | 1013 std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
1044 unsigned countResource(const MCSchedClassDesc *SC, unsigned PIdx,
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 74 const MCSchedClassDesc *SC) const { in mustBeginGroup()
85 const MCSchedClassDesc *SC) const { in mustEndGroup()
96 const MCSchedClassDesc *SC) const { in getNumMicroOps()
120 const MCSchedClassDesc *TargetSchedModel::
124 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
201 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
213 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
240 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { in computeInstrLatency()
266 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); in computeInstrLatency()
296 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOutputLatency()
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| H A D | MachineCombiner.cpp | 117 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
418 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) { in instr2instrSC()
422 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
443 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC; in preservesResourceLen()
444 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC; in preservesResourceLen()
449 ArrayRef<const MCSchedClassDesc *> MSCInsArr{InsInstrsSC}; in preservesResourceLen()
450 ArrayRef<const MCSchedClassDesc *> MSCDelArr{DelInstrsSC}; in preservesResourceLen()
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| H A D | MachineTraceMetrics.cpp | 121 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
1230 ArrayRef<const MCSchedClassDesc *> ExtraInstrs, in getResourceLength()
1231 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const { in getResourceLength()
1238 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs, in getResourceLength()
1242 for (const MCSchedClassDesc *SC : Instrs) { in getResourceLength()
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| H A D | MachineScheduler.cpp | 1015 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceTopDown()
1046 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceTopDown()
1097 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceBottomUp()
1128 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpScheduleTraceBottomUp()
2288 const MCSchedClassDesc *SC = DAG->getSchedClass(&SU); in init()
2376 SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx, in getNextResourceCycle()
2479 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2641 unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx, in countResource()
2692 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2978 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
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| H A D | MachinePipeliner.cpp | 1146 const MCSchedClassDesc *SCDesc = in minFuncUnits()
1189 const MCSchedClassDesc *SCDesc = in calcCriticalResources()
3558 const MCSchedClassDesc *SCDesc = DAG->getSchedClass(&SU); in canReserveResources()
3584 const MCSchedClassDesc *SCDesc = DAG->getSchedClass(&SU); in reserveResources()
3603 void ResourceManager::reserveResources(const MCSchedClassDesc *SCDesc, in reserveResources()
3615 void ResourceManager::unreserveResources(const MCSchedClassDesc *SCDesc, in unreserveResources()
3717 const MCSchedClassDesc *SCDesc = DAG->getSchedClass(&SU); in calculateResMII()
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| H A D | ScheduleDAGInstrs.cpp | 605 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
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| /src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSchedule.h | 118 struct MCSchedClassDesc { struct
320 const MCSchedClassDesc *SchedClassTable;
360 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc()
369 const MCSchedClassDesc &SCDesc);
378 const MCSchedClassDesc &SCDesc);
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| H A D | MCSubtargetInfo.h | 168 const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
172 const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
176 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, in getWriteLatencyEntry()
184 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
206 getReadAdvanceEntries(const MCSchedClassDesc &SC) const { in getReadAdvanceEntries()
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| /src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 43 const MCSchedClassDesc &SCDesc) { in computeInstrLatency()
60 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
73 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
91 const MCSchedClassDesc &SCDesc) { in getReciprocalThroughput()
116 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
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| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.cpp | 47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
171 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpSU()
272 const MCSchedClassDesc *SC = getSchedClass(SU); in EmitInstruction()
341 const MCSchedClassDesc *SC = getSchedClass(SU); in groupingCost()
390 const MCSchedClassDesc *SC = getSchedClass(SU); in resourcesCost()
418 const MCSchedClassDesc *SC = SchedModel->resolveSchedClass(MI); in emitInstruction()
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| H A D | SystemZHazardRecognizer.h | 121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
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| H A D | SystemZMachineScheduler.cpp | 254 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU); in releaseTopNode()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 87 const MCSchedClassDesc *PairSCDesc = in shouldAddSTPToBlock()
91 const MCSchedClassDesc *SingleSCDesc = in shouldAddSTPToBlock()
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| H A D | AArch64SIMDInstrOpt.cpp | 230 const MCSchedClassDesc *SCDesc = in shouldReplaceInst()
235 const MCSchedClassDesc *SCDescRepl; in shouldReplaceInst()
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| /src/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 44 const MCSchedClassDesc &SCDesc, in initializeUsedResources()
223 const MCSchedClassDesc &SCDesc, in computeMaxLatency()
272 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in populateWrites()
587 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in createInstrDescImpl()
588 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in createInstrDescImpl()
703 const MCSchedClassDesc &SCDesc = in createInstruction()
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| /src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 59 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
1052 std::vector<MCSchedClassDesc> &SCTab = in GenSchedClassTables()
1061 MCSchedClassDesc &SCDesc = SCTab.emplace_back(); in GenSchedClassTables()
1081 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; in GenSchedClassTables()
1127 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1157 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1275 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1299 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in GenSchedClassTables()
1415 std::vector<MCSchedClassDesc> &SCTab = in EmitSchedClassTables()
1428 << MCSchedClassDesc::InvalidNumMicroOps in EmitSchedClassTables()
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| /src/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 508 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in collectWrites()
576 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in checkRAWHazards()
639 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in addRegisterRead()
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| /src/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | InstructionInfoView.cpp | 134 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in collectData()
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| /src/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 210 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()
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