| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsOptionRecord.h | 66 const MCRegisterClass *GPR32RegClass;
67 const MCRegisterClass *GPR64RegClass;
68 const MCRegisterClass *FGR32RegClass;
69 const MCRegisterClass *FGR64RegClass;
70 const MCRegisterClass *AFGR64RegClass;
71 const MCRegisterClass *MSA128BRegClass;
72 const MCRegisterClass *COP0RegClass;
73 const MCRegisterClass *COP2RegClass;
74 const MCRegisterClass *COP3RegClass;
|
| /src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 35 class MCRegisterClass {
148 using regclass_iterator = const MCRegisterClass *;
164 const MCRegisterClass *Classes; // Pointer to the regclass array
274 unsigned PC, const MCRegisterClass *C, unsigned NC, in InitMCRegisterInfo()
381 const MCRegisterClass *RC) const;
451 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass()
456 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName()
|
| /src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 441 const MCRegisterClass &GPR32RC = MRI.getRegClass(AArch64::GPR32RegClassID); in clearsSuperRegisters()
443 const MCRegisterClass &FPR8RC = MRI.getRegClass(AArch64::FPR8RegClassID); in clearsSuperRegisters()
444 const MCRegisterClass &FPR16RC = MRI.getRegClass(AArch64::FPR16RegClassID); in clearsSuperRegisters()
445 const MCRegisterClass &FPR32RC = MRI.getRegClass(AArch64::FPR32RegClassID); in clearsSuperRegisters()
446 const MCRegisterClass &FPR64RC = MRI.getRegClass(AArch64::FPR64RegClassID); in clearsSuperRegisters()
447 const MCRegisterClass &FPR128RC = in clearsSuperRegisters()
|
| H A D | AArch64InstPrinter.cpp | 1694 const MCRegisterClass &FPR128RC = in printVectorList()
|
| /src/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMIChecking.cpp | 109 const MCRegisterClass *GPR64RegClass = in hasLiveDefs()
|
| /src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 109 const MCRegisterClass *RC) const { in getMatchingSuperReg()
|
| /src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
546 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); in clearsSuperRegisters()
547 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); in clearsSuperRegisters()
548 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); in clearsSuperRegisters()
|
| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 31 class MCRegisterClass; variable
1348 unsigned getRegBitWidth(const MCRegisterClass &RC);
|
| H A D | AMDGPUBaseInfo.cpp | 2234 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); in isSGPR()
2540 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth()
|
| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 52 const MCRegisterClass *MC;
|
| /src/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 169 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); in addRegisterFile()
|
| /src/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 83 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; in toDREG()
|
| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2833 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
4728 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()
4768 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()
4769 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
4888 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
|
| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 811 const MCRegisterClass RC = MRI.getRegClass(RCID); in printRegularOperand()
|
| /src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 292 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); in printInst()
|
| /src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3424 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()
3425 const MCRegisterClass *RC_out = in addMVEVecListOperands()
4639 const MCRegisterClass *RC; in parseRegisterList()
5029 const MCRegisterClass *RC = (Spacing == 1) ? in parseVectorList()
6944 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()
7409 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
|
| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 835 const MCRegisterClass &ConversionRC = in convertTrue16OpSel()
|
| /src/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 7884 const MCRegisterClass &WRegClass = in tryParseGPRSeqPair()
7886 const MCRegisterClass &XRegClass = in tryParseGPRSeqPair()
|