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Searched refs:MCRegister (Results 1 – 25 of 273) sorted by relevance

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/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h73 bool contains(MCRegister Reg) const { in contains()
83 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
162 MCRegister RAReg; // Return address register
163 MCRegister PCReg; // Program counter register
187 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
188 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
238 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
242 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const;
246 iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const;
250 iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const;
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H A DMCRegister.h33 class MCRegister {
34 friend hash_code hash_value(const MCRegister &);
38 constexpr MCRegister(unsigned Val = 0) : Reg(Val) {} in Reg()
74 static MCRegister from(unsigned Val) { in from()
76 return MCRegister(Val); in from()
84 constexpr bool operator==(const MCRegister &Other) const {
87 constexpr bool operator!=(const MCRegister &Other) const {
109 template <> struct DenseMapInfo<MCRegister> {
116 static unsigned getHashValue(const MCRegister &Val) {
119 static bool isEqual(const MCRegister &LHS, const MCRegister &RHS) {
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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegister.h24 constexpr Register(MCRegister Val) : Reg(Val) {} in Register()
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
49 constexpr bool isStack() const { return MCRegister::isStackSlot(Reg); } in isStack()
54 return int(Reg - MCRegister::FirstStackSlot); in stackSlot2Index()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
66 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
72 return Reg & MCRegister::VirtualRegFlag; in isVirtualRegister()
79 return Reg & ~MCRegister::VirtualRegFlag; in virtReg2Index()
86 return Index | MCRegister::VirtualRegFlag; in index2VirtReg()
105 constexpr operator MCRegister() const { return MCRegister(Reg); } in MCRegister() function
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H A DReachingDefAnalysis.h142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
146 MCRegister PhysReg) const;
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
155 MCRegister PhysReg) const;
160 MCRegister PhysReg) const;
172 bool hasLocalDefBefore(MachineInstr *MI, MCRegister PhysReg) const;
176 bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) const;
179 bool isRegDefinedAfter(MachineInstr *MI, MCRegister PhysReg) const;
183 int getClearance(MachineInstr *MI, MCRegister PhysReg) const;
187 void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg,
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H A DLiveRegMatrix.h108 MCRegister PhysReg);
115 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
120 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
128 bool isPhysRegUsed(MCRegister PhysReg) const;
141 MCRegister PhysReg = MCRegister::NoRegister);
147 MCRegister PhysReg);
153 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
H A DTargetRegisterInfo.h89 MCRegister getRegister(unsigned i) const { in getRegister()
350 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
357 const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
382 bool isInAllocatableClass(MCRegister RegNo) const { in isInAllocatableClass()
458 bool hasRegUnit(MCRegister Reg, Register RegUnit) const { in hasRegUnit()
562 explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const { in explainReservedReg()
569 MCRegister PhysReg) const { in isAsmClobberable()
581 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; } in isConstantPhysReg()
596 virtual bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const { in shouldAnalyzePhysregInMachineLoopInfo()
605 virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, in isCallerPreservedPhysReg()
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H A DCallingConvLower.h256 bool isAllocated(MCRegister Reg) const { in isAllocated()
307 bool IsShadowAllocatedReg(MCRegister Reg) const;
330 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
332 return MCRegister(); in AllocateReg()
338 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
340 return MCRegister(); in AllocateReg()
352 return MCRegister(); // Didn't find the reg. in AllocateReg()
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
393 return MCRegister(); // Didn't find the reg. in AllocateReg()
396 MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
H A DMachineRegisterInfo.h150 std::vector<std::pair<MCRegister, Register>> LiveIns;
249 void disableCalleeSavedRegister(MCRegister Reg);
639 bool isConstantPhysReg(MCRegister PhysReg) const;
861 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, in updateDbgUsersToReg()
893 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
899 bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
928 void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) { in reserveReg()
946 bool canReserveReg(MCRegister PhysReg) const { in canReserveReg()
964 bool isReserved(MCRegister PhysReg) const { in isReserved()
982 bool isAllocatable(MCRegister PhysReg) const { in isAllocatable()
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/src/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp28 MCRegister Reg;
36 MCRegAliasIteratorImpl(MCRegister Reg, const MCRegisterInfo *MCRI) in MCRegAliasIteratorImpl()
52 MCRegister operator*() const { in operator *()
107 MCRegister
108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
116 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg()
130 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, in getSubRegIndex()
131 MCRegister SubReg) const { in getSubRegIndex()
144 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum()
190 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
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/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocGreedy.h164 SmallVector<std::pair<const LiveInterval *, MCRegister>, 8>;
224 MCRegister PhysReg;
236 void reset(InterferenceCache &Cache, MCRegister Reg) { in reset()
295 MCRegister selectOrSplit(const LiveInterval &,
315 MCRegister selectOrSplitImpl(const LiveInterval &,
334 void calcGapWeights(MCRegister, SmallVectorImpl<float> &);
335 void evictInterference(const LiveInterval &, MCRegister,
337 bool mayRecolorAllInterferences(MCRegister PhysReg,
342 MCRegister tryAssign(const LiveInterval &, AllocationOrder &,
344 MCRegister tryEvict(const LiveInterval &, AllocationOrder &,
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H A DRegAllocEvictionAdvisor.h107 virtual MCRegister tryFindEvictionCandidate(
114 canEvictHintInterference(const LiveInterval &VirtReg, MCRegister PhysReg,
119 bool isUnusedCalleeSavedReg(MCRegister PhysReg) const;
124 bool canReassign(const LiveInterval &VirtReg, MCRegister FromReg) const;
135 bool canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const;
210 MCRegister tryFindEvictionCandidate(const LiveInterval &,
213 bool canEvictHintInterference(const LiveInterval &, MCRegister,
215 bool canEvictInterferenceBasedOnCost(const LiveInterval &, MCRegister, bool,
H A DLiveRegMatrix.cpp81 const LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit()
104 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
138 bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const { in isPhysRegUsed()
147 MCRegister PhysReg) { in checkRegMaskInterference()
165 MCRegister PhysReg) { in checkRegUnitInterference()
179 MCRegister RegUnit) { in query()
187 MCRegister PhysReg) { in checkInterference()
201 [&](MCRegister Unit, const LiveRange &LR) { in checkInterference()
211 MCRegister PhysReg) { in checkInterference()
247 return MCRegister::NoRegister; in getOneVReg()
H A DReachingDefAnalysis.cpp33 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg, in isValidRegUseOf()
44 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg, in isValidRegDefOf()
263 MCRegister PhysReg) const { in getReachingDef()
284 MCRegister PhysReg) const { in getReachingLocalMIDef()
291 MCRegister PhysReg) const { in hasSameReachingDef()
320 MCRegister PhysReg) const { in getClearance()
326 MCRegister PhysReg) const { in hasLocalDefBefore()
331 MCRegister PhysReg, in getReachingLocalUses()
356 MCRegister PhysReg, in getLiveInUses()
374 void ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, MCRegister PhysReg, in getGlobalUses()
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H A DMachineCopyPropagation.cpp112 SmallVector<MCRegister, 4> DefRegs;
121 void markRegsUnavailable(ArrayRef<MCRegister> Regs, in markRegsUnavailable()
123 for (MCRegister Reg : Regs) { in markRegsUnavailable()
134 void invalidateRegister(MCRegister Reg, const TargetRegisterInfo &TRI, in invalidateRegister()
166 void clobberRegister(MCRegister Reg, const TargetRegisterInfo &TRI, in clobberRegister()
180 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in clobberRegister()
181 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in clobberRegister()
233 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in trackCopy()
234 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in trackCopy()
277 MachineInstr *findAvailBackwardCopy(MachineInstr &I, MCRegister Reg, in findAvailBackwardCopy()
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H A DInterferenceCache.h47 MCRegister PhysReg = 0;
105 PhysReg = MCRegister::NoRegister; in clear()
111 MCRegister getPhysReg() const { return PhysReg; } in getPhysReg()
123 void reset(MCRegister physReg, LiveIntervalUnion *LIUArray,
155 Entry *get(MCRegister PhysReg);
209 void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) { in setPhysReg()
H A DRegAllocBasic.cpp99 MCRegister selectOrSplit(const LiveInterval &VirtReg,
118 bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg,
207 MCRegister PhysReg, in spillInterferences()
255 MCRegister RABasic::selectOrSplit(const LiveInterval &VirtReg, in selectOrSplit()
258 SmallVector<MCRegister, 8> PhysRegSpillCands; in selectOrSplit()
263 for (MCRegister PhysReg : Order) { in selectOrSplit()
283 for (MCRegister &PhysReg : PhysRegSpillCands) { in selectOrSplit()
H A DRegAllocEvictionAdvisor.cpp169 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference()
187 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost()
276 MCRegister DefaultEvictionAdvisor::tryFindEvictionCandidate( in tryFindEvictionCandidate()
282 MCRegister BestPhys; in tryFindEvictionCandidate()
285 return MCRegister::NoRegister; in tryFindEvictionCandidate()
297 MCRegister PhysReg = *I; in tryFindEvictionCandidate()
H A DRegAllocGreedy.cpp397 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg, in tryAssign()
401 MCRegister PhysReg; in tryAssign()
420 MCRegister PhysHint = Hint.asMCReg(); in tryAssign()
447 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign()
456 MCRegister FromReg) const { in canReassign()
463 for (MCRegister Reg : in canReassign()
482 MCRegister PhysReg, in evictInterference()
522 bool RegAllocEvictionAdvisor::isUnusedCalleeSavedReg(MCRegister PhysReg) const { in isUnusedCalleeSavedReg()
523 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
558 MCRegister PhysReg) const { in canAllocatePhysReg()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h51 void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
77 MCRegister getAlignedHighSGPRForRC(const MachineFunction &MF,
83 MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
87 MCRegister PhysReg) const override;
177 StringRef getRegAsmName(MCRegister Reg) const override;
180 unsigned getHWRegIndex(MCRegister Reg) const { in getHWRegIndex()
284 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI,
331 MCRegister getReturnAddressReg(const MachineFunction &MF) const;
359 MCRegister getVCC() const;
361 MCRegister getExec() const;
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38 bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const;
99 MCRegister PhysReg) const override;
101 MCRegister PhysReg) const override;
129 MCRegister Reg) const override;
149 bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override;
/src/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp46 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
47 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
86 void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
173 MCRegister RegNum;
194 void setReg(MCRegister PhysReg) { Reg.RegNum = PhysReg; } in setReg()
518 MCRegister getReg() const override { in getReg()
534 auto RegName = [](MCRegister Reg) { in print()
605 static MCRegister convertFPR32ToFPR64(MCRegister Reg) { in convertFPR32ToFPR64()
613 static bool matchRegisterNameHelper(MCRegister &RegNo, StringRef Name) { in matchRegisterNameHelper()
627 bool LoongArchAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, in parseRegister()
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/src/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.h33 static const char *getRegisterName(MCRegister Reg);
36 void printAddress(const MCAsmInfo *MAI, MCRegister Base,
37 const MCOperand &DispMO, MCRegister Index, raw_ostream &O);
42 void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg,
46 void printRegName(raw_ostream &O, MCRegister Reg) const override;
/src/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp79 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
87 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRX1X5RegisterClass()
101 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR16RegisterClass()
112 MCRegister Reg = RISCV::F0_F + RegNo; in DecodeFPR32RegisterClass()
123 MCRegister Reg = RISCV::F8_F + RegNo; in DecodeFPR32CRegisterClass()
134 MCRegister Reg = RISCV::F0_D + RegNo; in DecodeFPR64RegisterClass()
145 MCRegister Reg = RISCV::F8_D + RegNo; in DecodeFPR64CRegisterClass()
176 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
187 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRPairRegisterClass()
198 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18); in DecodeSR07RegisterClass()
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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchInstPrinter.h31 void printRegName(raw_ostream &O, MCRegister Reg) const override;
44 static const char *getRegisterName(MCRegister Reg);
45 static const char *getRegisterName(MCRegister Reg, unsigned AltIdx);
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h95 MCRegister PhysReg) const override;
96 bool isCallerPreservedPhysReg(MCRegister PhysReg,
150 static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
151 MCRegister SrcReg);
175 bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override { in isNonallocatableRegisterCalleeSave()

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