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Searched refs:LoadLatency (Results 1 – 25 of 91) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleZnver3.td45 let LoadLatency = 4;
450 Znver3Model.LoadLatency,
477 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
493 defm : Zn3WriteResInt<WriteLoad, [Zn3AGU012, Zn3Load], !add(Znver3Model.LoadLatency, 1), [1, 1], 1>;
497 defm : Zn3WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver3Model.LoadLatency, 1), [], 0>;
500 let Latency = !add(Znver3Model.LoadLatency, 1);
514 let Latency = Znver3Model.LoadLatency;
624 defm : Zn3WriteResInt<WriteIMulHLd, [], !add(4, Znver3Model.LoadLatency), [], 0>; // Integer multi…
642 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
670 let Latency = !add(Znver3Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
[all …]
H A DX86ScheduleZnver4.td41 let LoadLatency = 4;
453 Znver4Model.LoadLatency,
488 def : ReadAdvance<ReadAfterLd, Znver4Model.LoadLatency>;
504 defm : Zn4WriteResInt<WriteLoad, [Zn4AGU012, Zn4Load], !add(Znver4Model.LoadLatency, 1), [1, 1], 1>;
508 defm : Zn4WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver4Model.LoadLatency, 1), [], 0>;
511 let Latency = !add(Znver4Model.LoadLatency, 1);
525 let Latency = Znver4Model.LoadLatency;
635 defm : Zn4WriteResInt<WriteIMulHLd, [], !add(4, Znver4Model.LoadLatency), [], 0>; // Integer multi…
653 let Latency = !add(Znver4Model.LoadLatency, Zn4WriteCMPXCHG8rr.Latency);
681 let Latency = !add(Znver4Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
[all …]
/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kSchedule.td17 let LoadLatency = 4; // Word (Rn)
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV71.td32 let LoadLatency = 1;
H A DHexagonScheduleV62.td30 let LoadLatency = 1;
H A DHexagonScheduleV69.td33 let LoadLatency = 1;
H A DHexagonScheduleV73.td32 let LoadLatency = 1;
H A DHexagonScheduleV66.td33 let LoadLatency = 1;
H A DHexagonScheduleV5.td39 let LoadLatency = 1;
H A DHexagonScheduleV55.td41 let LoadLatency = 1;
H A DHexagonScheduleV67.td33 let LoadLatency = 1;
H A DHexagonScheduleV68.td32 let LoadLatency = 1;
H A DHexagonScheduleV65.td33 let LoadLatency = 1;
H A DHexagonScheduleV71T.td53 let LoadLatency = 1;
H A DHexagonScheduleV67T.td55 let LoadLatency = 1;
H A DHexagonScheduleV60.td74 let LoadLatency = 1;
/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td28 let LoadLatency = 2;
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp139 ? getSchedModel().LoadLatency + 1 in getMaxBuildIntsCost()
H A DRISCVSchedSyntacoreSCR1.td21 let LoadLatency = 2;
H A DRISCVSchedSyntacoreSCR3.td19 let LoadLatency = 2;
/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h294 unsigned LoadLatency; member
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleA2.td160 let LoadLatency = 6; // Optimistic load latency assuming bypass.
H A DPPCScheduleG5.td119 let LoadLatency = 3; // Optimistic load latency assuming bypass.
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td22 let LoadLatency = 3; // Optimistic load latency.
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td16 let LoadLatency = 2; // Latency when not pipelined, not pc-relative

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