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Searched refs:LaneBitmask (Results 1 – 25 of 60) sorted by relevance

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/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DLaneBitmask.h40 struct LaneBitmask { struct
46 constexpr LaneBitmask() = default; argument
47 explicit constexpr LaneBitmask(Type V) : Mask(V) {} in LaneBitmask() function
49 constexpr bool operator== (LaneBitmask M) const { return Mask == M.Mask; }
50 constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
51 constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; }
56 constexpr LaneBitmask operator~() const { argument
57 return LaneBitmask(~Mask);
59 constexpr LaneBitmask operator|(LaneBitmask M) const {
60 return LaneBitmask(Mask | M.Mask);
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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDetectDeadLanes.h47 LaneBitmask UsedLanes;
48 LaneBitmask DefinedLanes;
69 void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
74 void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
80 LaneBitmask DefinedLanes);
86 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
87 LaneBitmask DefinedLanes) const;
91 LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
95 LaneBitmask determineInitialDefinedLanes(unsigned Reg);
96 LaneBitmask determineInitialUsedLanes(unsigned Reg);
H A DRegisterPressure.h40 LaneBitmask LaneMask;
42 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
265 LaneBitmask LaneMask;
267 IndexMaskPair(unsigned Index, LaneBitmask LaneMask) in IndexMaskPair()
296 LaneBitmask contains(Register Reg) const { in contains()
300 return LaneBitmask::getNone(); in contains()
306 LaneBitmask insert(RegisterMaskPair Pair) { in insert()
310 LaneBitmask PrevMask = InsertRes.first->LaneMask; in insert()
314 return LaneBitmask::getNone(); in insert()
319 LaneBitmask erase(RegisterMaskPair Pair) { in erase()
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H A DTargetRegisterInfo.h55 const LaneBitmask LaneMask;
211 LaneBitmask getLaneMask() const { in getLaneMask()
261 const LaneBitmask *SubRegIndexLaneMasks;
264 LaneBitmask CoveringLanes;
273 const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes,
408 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
419 LaneBitmask LaneMask,
445 LaneBitmask getCoveringLanes() const { return CoveringLanes; } in getCoveringLanes()
711 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, in composeSubRegIndexLaneMask()
712 LaneBitmask Mask) const { in composeSubRegIndexLaneMask()
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H A DRDFRegisters.h90 LaneBitmask Mask = LaneBitmask::getNone(); // Only for registers.
94 LaneBitmask M = LaneBitmask::getAll())
95 : Reg(R), Mask(isRegId(R) && R != 0 ? M : LaneBitmask::getNone()) {} in Reg()
110 std::hash<LaneBitmask::Type>{}(Mask.getAsInteger()); in hash()
187 LaneBitmask Mask;
239 using MapType = std::map<RegisterId, LaneBitmask>;
317 PrintLaneMaskShort(LaneBitmask M) : Mask(M) {} in PrintLaneMaskShort()
318 LaneBitmask Mask;
H A DLiveIntervalCalc.h39 void extendToUses(LiveRange &LR, Register Reg, LaneBitmask LaneMask,
55 extendToUses(LR, PhysReg, LaneBitmask::getAll()); in extendToUses()
H A DScheduleDAGInstrs.h54 LaneBitmask LaneMask;
57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, in VReg2SUnitOperIdx()
379 LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const;
H A DRegisterScavenging.h147 void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
H A DLiveInterval.h697 LaneBitmask LaneMask;
700 SubRange(LaneBitmask LaneMask) : LaneMask(LaneMask) {} in SubRange()
703 SubRange(LaneBitmask LaneMask, const LiveRange &Other, in SubRange()
793 LaneBitmask LaneMask) { in createSubRange()
802 LaneBitmask LaneMask, in createSubRangeFrom()
834 LaneBitmask LaneMask,
877 void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
H A DLiveRegUnits.h93 void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) { in addRegMasked()
95 LaneBitmask UnitMask = (*Unit).second; in addRegMasked()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterPressure.cpp52 LaneBitmask PrevMask, LaneBitmask NewMask) { in increaseSetPressure()
66 LaneBitmask PrevMask, LaneBitmask NewMask) { in decreaseSetPressure()
156 LaneBitmask PreviousMask, in increaseRegPressure()
157 LaneBitmask NewMask) { in increaseRegPressure()
171 LaneBitmask PreviousMask, in decreaseRegPressure()
172 LaneBitmask NewMask) { in decreaseRegPressure()
366 LaneBitmask::getNone(), Pair.LaneMask); in initLiveThru()
370 static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits, in getRegLanes()
376 return LaneBitmask::getNone(); in getRegLanes()
400 RegUnits.push_back(RegisterMaskPair(RegUnit, LaneBitmask::getNone())); in setRegZero()
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H A DDetectDeadLanes.cpp109 LaneBitmask UsedLanes) { in addUsedLanesOnOperand()
123 LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes; in addUsedLanesOnOperand()
135 LaneBitmask UsedLanes) { in transferUsedLanesStep()
139 LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO); in transferUsedLanesStep()
144 LaneBitmask
146 LaneBitmask UsedLanes, in transferUsedLanes()
163 LaneBitmask MO2UsedLanes = in transferUsedLanes()
171 LaneBitmask MO1UsedLanes; in transferUsedLanes()
191 LaneBitmask DefinedLanes) { in transferDefinedLanesStep()
217 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
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H A DLiveIntervalCalc.cpp60 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
65 LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg); in calculate()
102 extendToUses(LI, Reg, LaneBitmask::getAll()); in calculate()
120 extendToUses(MainRange, LI.reg(), LaneBitmask::getAll(), &LI); in constructMainRangeFromSubranges()
136 LaneBitmask Mask, LiveInterval *LI) { in extendToUses()
160 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DRDFRegisters.cpp57 UnitInfos[U].Mask = LaneBitmask::getAll(); in PhysicalRegisterInfo()
61 std::pair<uint32_t, LaneBitmask> P = *I; in PhysicalRegisterInfo()
172 LaneBitmask RCM = in mapTo()
173 RI.RegClass ? RI.RegClass->LaneMask : LaneBitmask::getAll(); in mapTo()
174 LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask); in mapTo()
284 std::pair<uint32_t, LaneBitmask> P = *U; in hasAliasOf()
299 std::pair<uint32_t, LaneBitmask> P = *U; in hasCoverOf()
314 std::pair<uint32_t, LaneBitmask> P = *U; in insert()
385 LaneBitmask M; in makeRegRef()
387 std::pair<uint32_t, LaneBitmask> P = *I; in makeRegRef()
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H A DRegisterCoalescer.cpp158 LaneBitmask ShrinkMask;
232 LaneBitmask PrunedLanes);
264 LaneBitmask LaneMask, CoalescerPair &CP,
270 LaneBitmask LaneMask, const CoalescerPair &CP);
982 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg()); in removeCopyByCommutingDef()
985 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntB.reg()); in removeCopyByCommutingDef()
989 LaneBitmask MaskA; in removeCopyByCommutingDef()
1522 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg); in reMaterializeTrivialDef()
1546 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx); in reMaterializeTrivialDef()
1690 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx); in eliminateUndefCopy()
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H A DScheduleDAGInstrs.cpp377 LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const in getLaneMaskForMO()
383 return LaneBitmask::getAll(); in getLaneMaskForMO()
409 LaneBitmask DefLaneMask; in addVRegDefDeps()
410 LaneBitmask KillLaneMask; in addVRegDefDeps()
416 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; in addVRegDefDeps()
433 DefLaneMask = LaneBitmask::getAll(); in addVRegDefDeps()
434 KillLaneMask = LaneBitmask::getAll(); in addVRegDefDeps()
444 LaneBitmask LaneMask = I->LaneMask; in addVRegDefDeps()
483 LaneBitmask LaneMask = DefLaneMask; in addVRegDefDeps()
506 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask; in addVRegDefDeps()
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H A DLiveInterval.cpp873 LaneBitmask LaneMask, in stripValuesNotDefiningMask()
898 LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg()); in stripValuesNotDefiningMask()
899 LaneBitmask ExpectedDefMask = in stripValuesNotDefiningMask()
920 BumpPtrAllocator &Allocator, LaneBitmask LaneMask, in refineSubRanges()
924 LaneBitmask ToApply = LaneMask; in refineSubRanges()
926 LaneBitmask SRMask = SR.LaneMask; in refineSubRanges()
927 LaneBitmask Matching = SRMask & LaneMask; in refineSubRanges()
966 LaneBitmask LaneMask, in computeSubRangeUndefs()
970 LaneBitmask VRegMask = MRI.getMaxLaneMaskForVReg(reg()); in computeSubRangeUndefs()
978 LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg); in computeSubRangeUndefs()
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H A DLiveIntervals.cpp390 Register Reg, LaneBitmask LaneMask) { in extendSegmentsToUses()
396 auto getSubRange = [](const LiveInterval &I, LaneBitmask M) in extendSegmentsToUses()
516 extendSegmentsToUses(NewLR, WorkList, Reg, LaneBitmask::getNone()); in shrinkToUses()
586 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
780 LaneBitmask DefinedLanesMask; in addKillFlags()
783 DefinedLanesMask = LaneBitmask::getNone(); in addKillFlags()
794 DefinedLanesMask = LaneBitmask::getAll(); in addKillFlags()
803 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1045 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1053 updateRange(LI, Reg, LaneBitmask::getNone()); in updateAllRanges()
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H A DMachineInstrBundle.cpp307 std::pair<LaneBitmask, LaneBitmask>
312 LaneBitmask UseMask, DefMask; in AnalyzeVirtRegLanesInBundle()
322 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in AnalyzeVirtRegLanesInBundle()
H A DTargetRegisterInfo.cpp56 const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, in TargetRegisterInfo()
57 LaneBitmask SRICoveringLanes, const RegClassInfo *const RCIs, in TargetRegisterInfo()
517 LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const { in getCoveringSubRegIndexes()
526 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx); in getCoveringSubRegIndexes()
553 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx); in getCoveringSubRegIndexes()
558 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx); in getCoveringSubRegIndexes()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp51 LaneBitmask PrevMask, in inc()
52 LaneBitmask NewMask, in inc()
245 static LaneBitmask getDefRegMask(const MachineOperand &MO, in getDefRegMask()
274 LaneBitmask UseMask; in collectVirtualRegUses()
294 LaneBitmask llvm::getLiveLaneMask(unsigned Reg, SlotIndex SI, in getLiveLaneMask()
300 LaneBitmask llvm::getLiveLaneMask(const LiveInterval &LI, SlotIndex SI, in getLiveLaneMask()
302 LaneBitmask LiveMask; in getLiveLaneMask()
373 LaneBitmask DefMask = getDefRegMask(MO, *MRI); in recede()
377 ECDefPressure.inc(Reg, LaneBitmask::getNone(), DefMask, *MRI); in recede()
380 DefPressure.inc(Reg, LaneBitmask::getNone(), DefMask, *MRI); in recede()
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H A DGCNRegPressure.h69 LaneBitmask PrevMask,
70 LaneBitmask NewMask,
148 using LiveRegSet = DenseMap<unsigned, LaneBitmask>;
262 LaneBitmask getLiveLaneMask(unsigned Reg,
267 LaneBitmask getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
334 Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI); in getRegPressure()
H A DSIFormMemoryClauses.cpp35 using RegUse = DenseMap<unsigned, std::pair<unsigned, LaneBitmask>>;
176 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg()); in canBundle()
225 LaneBitmask Mask = Reg.isVirtual() in collectRegUses()
227 : LaneBitmask::getAll(); in collectRegUses()
360 LaneBitmask KilledMask; in runOnMachineFunction()
/src/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h53 LaneBitmask Mask;
73 mutable LaneBitmask LaneMask;
156 LaneBitmask computeLaneMask() const;
250 typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
259 ArrayRef<LaneBitmask> getRegUnitLaneMasks() const { in getRegUnitLaneMasks()
359 LaneBitmask LaneMask;
854 LaneBitmask CoveringLanes;
H A DCodeGenRegisters.cpp108 LaneBitmask CodeGenSubRegIndex::computeLaneMask() const { in computeLaneMask()
114 LaneMask = LaneBitmask::getAll(); in computeLaneMask()
117 LaneBitmask M; in computeLaneMask()
1569 CoveringLanes = LaneBitmask::getAll(); in computeSubRegLaneMasks()
1572 if (Bit > LaneBitmask::BitWidth) { in computeSubRegLaneMasks()
1577 Idx.LaneMask = LaneBitmask::getLane(Bit); in computeSubRegLaneMasks()
1580 Idx.LaneMask = LaneBitmask::getNone(); in computeSubRegLaneMasks()
1600 assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) && in computeSubRegLaneMasks()
1602 MaskRolPair MaskRol = {LaneBitmask::getLane(0), (uint8_t)DstBit}; in computeSubRegLaneMasks()
1616 LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit); in computeSubRegLaneMasks()
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