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Searched refs:LMul (Results 1 – 12 of 12) sorted by relevance

/src/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp193 unsigned LMul; in printVType() local
195 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); in printVType()
201 OS << LMul; in printVType()
215 unsigned LMul; in getSEWLMULRatio() local
217 std::tie(LMul, Fractional) = decodeVLMUL(VLMul); in getSEWLMULRatio()
220 LMul = Fractional ? (8 / LMul) : (LMul * 8); in getSEWLMULRatio()
223 return (SEW * 8) / LMul; in getSEWLMULRatio()
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td150 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
153 vti.LMul, vti.AVL, vti.RegClass,
166 vti.LMul, vti.AVL, vti.RegClass,
225 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
228 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
240 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
243 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
257 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
258 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX))
273 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
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H A DRISCVInstrInfoVVLPatterns.td877 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
881 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
894 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
908 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
912 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
928 vti.LMul, wti.RegClass, vti.RegClass>;
931 vti.Log2SEW, vti.LMul, wti.RegClass,
935 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
939 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
953 vti.Log2SEW, vti.LMul, vti.RegClass, wti.RegClass,
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H A DRISCVInstrInfoZvk.td200 …vs2_types = !cond(!eq(vd_lmul, "M8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)),
201 … !eq(vd_lmul, "M4") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)),
202 … !eq(vd_lmul, "M2") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 16)),
203 … !eq(vd_lmul, "M1") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 8)),
204 … !eq(vd_lmul, "MF2") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 4)),
205 … !eq(vd_lmul, "MF4") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 2)),
206 … !eq(vd_lmul, "MF8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 1)));
577 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX)
597 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
605 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
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H A DRISCVInstrInfoVPseudos.td262 LMULInfo LMul = M;
392 LMULInfo LMul = M;
1869 defvar mx = mti.LMul.MX;
1871 let VLMul = mti.LMul.value in {
1944 defvar mx = mti.LMul.MX;
1946 let VLMul = mti.LMul.value in {
1998 defvar mx = mti.LMul.MX;
1999 let VLMul = mti.LMul.value in {
2010 defvar mx = mti.LMul.MX;
2011 let VLMul = mti.LMul.value in {
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H A DRISCVInstrInfoXSf.td665 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
669 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
678 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
682 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
686 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
695 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
699 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
703 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
730 Vs2Info.Log2SEW, Vs2Info.LMul,
772 "Pseudo" # instruction # "_" # Vti.LMul.MX,
H A DRISCVSchedSiFiveP600.td384 foreach LMul = [1, 2, 4, 8] in {
385 let Latency = 8, ReleaseAtCycles = [LMul] in {
386 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP600VLD]>;
387 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP600VST]>;
389 let Latency = LMul, ReleaseAtCycles = [LMul] in {
390 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP600VectorArith]>;
H A DRISCVInsertVSETVLI.cpp327 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); in isLMUL1OrSmaller()
328 return Fractional || LMul == 1; in isLMUL1OrSmaller()
988 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMul); in computeVLMAX()
990 VLEN = VLEN / LMul; in computeVLMAX()
992 VLEN = VLEN * LMul; in computeVLMAX()
H A DRISCVISelLowering.h814 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
1095 void allocatePhysReg(unsigned NF = 1, unsigned LMul = 1,
H A DRISCVInstrInfo.cpp190 RISCVII::VLMUL LMul) { in isConvertibleToVMV_V_V() argument
224 if (FirstLMul != LMul) in isConvertibleToVMV_V_V()
256 return LMul == RISCVVType::getVLMUL(VType); in isConvertibleToVMV_V_V()
323 RISCVII::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags); in copyPhysRegVector() local
328 auto [LMulVal, Fractional] = RISCVVType::decodeVLMUL(LMul); in copyPhysRegVector()
401 if (LMul == LMulCopied && in copyPhysRegVector()
402 isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { in copyPhysRegVector()
H A DRISCVInstrInfoXTHead.td511 vti.Mask, wti.Log2SEW, vti.LMul,
524 vti.Mask, wti.Log2SEW, vti.LMul,
H A DRISCVISelLowering.cpp2475 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) { in getRegClassIDForLMUL() argument
2476 switch (LMul) { in getRegClassIDForLMUL()
2664 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); in useRVVForFixedLengthVectorVT() local
2666 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
2860 unsigned LMul; in getLMULCost() local
2862 std::tie(LMul, Fractional) = in getLMULCost()
2865 Cost = LMul <= DLenFactor ? (DLenFactor / LMul) : 1; in getLMULCost()
2867 Cost = (LMul * DLenFactor); in getLMULCost()
8977 SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT); in lowerGetVectorLength() local
8984 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, ID, AVL, Sew, LMul); in lowerGetVectorLength()
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