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Searched refs:LEA (Results 1 – 17 of 17) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ArgumentStackSlotRebase.cpp163 MachineInstr *LEA = in runOnMachineFunction() local
172 X86FI->setStackPtrSaveMI(LEA); in runOnMachineFunction()
H A DX86SchedPredicates.td28 // A predicate used to check if a LEA instruction uses all three source
59 // 3-operands LEA. Tablegen automatically generates a new method for it in
H A DX86ScheduleBtVer2.td36 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
935 // This write is used for slow LEA instructions.
940 // On Jaguar, a slow LEA is either a 3Ops LEA (base, index, offset), or an LEA
944 // A 3-operand LEA (base, index, offset).
946 // An LEA with a "Scale" different than 1.
H A DX86ScheduleBdVer2.td549 // This write is used for slow LEA instructions.
555 // On Piledriver, a slow LEA is either a 3Ops LEA (base, index, offset),
556 // or an LEA with a `Scale` value different than 1.
559 // A 3-operand LEA (base, index, offset).
561 // An LEA with a "Scale" different than 1.
H A DX86.td478 … "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;
503 // True if the LEA instruction inputs have to be ready at address generation
506 "LEA instruction needs inputs at AG stage">;
509 "LEA instruction with certain arguments is slow">;
511 // True if the LEA instruction has all three source operands: base, index,
512 // and offset or if the LEA instruction uses base and index registers where
515 "LEA instruction with 3 ops or certain registers is slow">;
H A DX86ScheduleZnver3.td573 defm : Zn3WriteResInt<WriteLEA, [Zn3AGU012], 1, [1], 1>; // LEA instructions can't fold loads.
575 // This write is used for slow LEA instructions.
582 // On Znver3, a slow LEA is either a 3Ops LEA (base, index, offset),
583 // or an LEA with a `Scale` value different than 1.
586 // A 3-operand LEA (base, index, offset).
588 // An LEA with a "Scale" different than 1.
H A DX86ScheduleZnver4.td584 defm : Zn4WriteResInt<WriteLEA, [Zn4AGU012], 1, [1], 1>; // LEA instructions can't fold loads.
586 // This write is used for slow LEA instructions.
593 // On Znver4, a slow LEA is either a 3Ops LEA (base, index, offset),
594 // or an LEA with a `Scale` value different than 1.
597 // A 3-operand LEA (base, index, offset).
599 // An LEA with a "Scale" different than 1.
H A DX86ScheduleAtom.td37 def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
H A DX86Schedule.td138 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
H A DX86SchedSkylakeClient.td163 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
H A DX86InstrCompiler.td1444 // 3-addressified into an LEA instruction to avoid copies. However, we also
1493 // ADD can be 3-addressified into an LEA instruction to avoid copies.
H A DX86SchedSkylakeServer.td164 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
H A DX86SchedIceLake.td171 def : WriteRes<WriteLEA, [ICXPort15]>; // LEA instructions can't fold loads.
H A DX86InstrArithmetic.td15 // LEA - Load Effective Address
/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.td999 // Section 8.2.1 - LEA
1002 let cx = 0 in defm LEA : RMm<"lea", 0x06, I64, /* MoveImm */ 1>;
1006 // LEA basic patterns.
1007 // Need to be defined here to prioritize LEA over ADX.
1617 // LEA patterns
1634 // 1. LEA %reg, label@LO32
1637 // 3. (LEA %reg, label@LO32)
1640 // 4. (LEA %reg, label@LO32)
/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrData.td17 /// LEA [~] PEA [ ] MOVE [~] MOVE16 [ ] MOVEA [ ]
438 // LEA
/src/share/misc/
H A Dpci_vendors3309 686a Vega 10 LEA