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Searched refs:LC1 (Results 1 – 17 of 17) sorted by relevance

/src/sys/dev/xdma/controller/
H A Dpl330.h63 #define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */ macro
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.h112 Hexagon::LC1 == R); in isLoopRegister()
H A DHexagonMCChecker.cpp51 Defs[Hexagon::LC1].insert(Unconditional); in init()
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
H A DHexagonRegisterInfo.cpp165 Reserved.set(Hexagon::LC1); // C3 in getReservedRegs()
H A DHexagonRegisterInfo.td176 def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;
207 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
560 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
H A DHexagonHardwareLoops.cpp1007 static const Register Regs01[] = { LC0, SA0, LC1, SA1 }; in isInvalidLoopOperation()
1008 static const Register Regs1[] = { LC1, SA1 }; in isInvalidLoopOperation()
H A DHexagonISelLowering.cpp330 .Case("lc1", Hexagon::LC1) in getRegisterByName()
H A DHexagonDepInstrInfo.td5033 let Uses = [LC0, LC1, SA0, SA1];
5034 let Defs = [LC0, LC1, P3, PC, USR];
5042 let Uses = [LC1, SA1];
5043 let Defs = [LC1, PC];
5681 let Defs = [LC1, SA1];
5699 let Defs = [LC1, SA1];
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp316 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; in softenSetCCOperands() local
321 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
327 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
333 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
339 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
345 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
351 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
359 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
368 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
380 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp675 /* 0 */ SA0, LC0, SA1, LC1, in DecodeCtrRegsRegisterClass()
/src/share/misc/
H A Dusb_vendors5515 5116 SCR331-LC1 / SCR3310 SmartCard Reader
11186 a107 USB to Memory Stick (LC1) Drive
11187 a109 LC1 CompactFlash & SmartMedia Card Reader
11188 a10b USB to CF+MS(LC1)
11196 b000 USB to CF(LC1)
11200 b00a USB to CF+SD Drive(LC1)
11201 b00b USB to Memory Stick(LC1)
17511 0010 LC1 Linear Camera (Jungo)
17514 0110 LC1 Linear Camera (VISA)
/src/contrib/libdiff/test/
H A Dtest010.left.txt8034 "CF + SM Combo (LC1)",
H A Dtest110.left-P.txt8034 "CF + SM Combo (LC1)",
H A Dtest110.right-P.txt8034 "CF + SM Combo (LC1)",
H A Dtest010.right.txt8034 "CF + SM Combo (LC1)",
/src/sys/dev/usb/
H A Dusbdevs3648 product ONSPEC CFSM_COMBO 0xa109 USB to CF + SM Combo (LC1)