Home
last modified time | relevance | path

Searched refs:L3 (Results 1 – 25 of 65) sorted by relevance

123

/src/lib/libc/i386/string/
H A Dstrcmp.S61 je L3
63 jne L3
68 je L3
70 jne L3
75 je L3
77 jne L3
82 je L3
84 jne L3
89 je L3
91 jne L3
[all …]
H A Dstrncmp.S69 jz L3
71 jne L3
91 jz L3
93 jne L3
101 jz L3
103 jne L3
111 jz L3
113 jne L3
121 jz L3
123 jne L3
[all …]
H A Dswab.S68 L3: lodsw label
93 jnz L3
/src/crypto/openssl/crypto/whrlpool/
H A Dwp_block.c529 u64 L0, L1, L2, L3, L4, L5, L6, L7; in whirlpool_block()
561 … L3 = C0(K, 3) ^ C1(K, 2) ^ C2(K, 1) ^ C3(K, 0) ^ C4(K, 7) ^ C5(K, 6) ^ C6(K, 5) ^ C7(K, 4); in whirlpool_block()
570 K.q[3] = L3; in whirlpool_block()
579 … L3 ^= C0(S, 3) ^ C1(S, 2) ^ C2(S, 1) ^ C3(S, 0) ^ C4(S, 7) ^ C5(S, 6) ^ C6(S, 5) ^ C7(S, 4); in whirlpool_block()
588 S.q[3] = L3; in whirlpool_block()
597 L3 = C3(K, 0); in whirlpool_block()
606 L3 ^= C2(K, 1); in whirlpool_block()
614 L3 ^= C1(K, 2); in whirlpool_block()
622 L3 ^= C0(K, 3); in whirlpool_block()
638 L3 ^= C7(K, 4); in whirlpool_block()
[all …]
/src/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-cpus.dtsi170 next-level-cache = <&L3>;
178 next-level-cache = <&L3>;
186 next-level-cache = <&L3>;
194 next-level-cache = <&L3>;
197 L3: l3-cache { label
/src/sys/contrib/device-tree/Bindings/edac/
H A Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
42 - reg : First resource shall be the L3 EDAC resource.
/src/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_rfgain.c126 uint32_t L1, L2, L3, L4; in ar5212InvalidGainReadback() local
132 L3 = 0; in ar5212InvalidGainReadback()
144 L3 = (gStep != 0x3f) ? 0x40 : L1; in ar5212InvalidGainReadback()
145 L4 = L3 + 50; in ar5212InvalidGainReadback()
153 return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4)); in ar5212InvalidGainReadback()
/src/contrib/libdiff/test/
H A Dexpect.results_test5 [1] minus lines L3 R0 @L 2 @R 2
11 [1] minus lines L3 R0 @L 2 @R 2
/src/sys/contrib/device-tree/Bindings/sound/
H A Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
H A Domap-mcpdm.txt7 <L3 interconnect address, size>;
18 <0x49032000 0x7f>; /* L3 Interconnect */
H A Domap-mcbsp.txt10 <L3 interconnect address, size>;
/src/sys/contrib/device-tree/Bindings/arm/omap/
H A Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/src/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
145 <0x49024000 0xff>; /* L3 Interconnect */
180 <0x49026000 0xff>; /* L3 Interconnect */
216 <0x4902a000 0x1000>; /* L3 data port */
252 <0x4902e000 0x7f>; /* L3 Interconnect */
314 <0x49032000 0x7f>; /* L3 Interconnect */
H A Domap5-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
145 <0x49024000 0xff>; /* L3 Interconnect */
180 <0x49026000 0xff>; /* L3 Interconnect */
234 <0x4902e000 0x7f>; /* L3 Interconnect */
277 <0x49032000 0x7f>; /* L3 Interconnect */
/src/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
H A Dgemini-wbd222.dts44 label = "wbd111:red:L3";
62 label = "wbd111:green:L3";
/src/sys/powerpc/powerpc/
H A Dswtch32.S162 beq .L3
166 .L3: label
H A Dswtch64.S221 beq .L3
226 .L3: label
/src/tools/tools/netmap/
H A DREADME8 lb an L3/L4 load balancer
/src/contrib/llvm-project/libcxx/include/
H A Dmutex169 template <class L1, class L2, class... L3>
170 int try_lock(L1&, L2&, L3&...);
171 template <class L1, class L2, class... L3>
172 void lock(L1&, L2&, L3&...);
/src/lib/msun/src/
H A De_powf.c35 L3 = 3.3333334327e-01, /* 0x3eaaaaab */ variable
177 r = s2*s2*(L1+s2*(L2+s2*(L3+s2*(L4+s2*(L5+s2*L6))))); in powf()
H A De_pow.c76 L3 = 3.33333329818377432918e-01, /* 0x3FD55555, 0x518F264D */ variable
234 r = s2*s2*(L1+s2*(L2+s2*(L3+s2*(L4+s2*(L5+s2*L6))))); in pow()
/src/sys/contrib/device-tree/Bindings/arm/
H A Darm-dsu-pmu.txt4 with a shared L3 memory system, control logic and external interfaces to
/src/sys/contrib/device-tree/Bindings/
H A Dresource-names.txt28 <1 0 0x49000000 0x00001000>; /* L3 path */
/src/sys/contrib/device-tree/Bindings/bus/
H A Dti-sysc.txt4 hardware for devices connected to various interconnects such as L3
54 parent L3 range for DMA access

123