| /src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 35 bool IsRet; member
41 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet, in RISCVOutgoingValueAssigner()
44 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet), in RISCVOutgoingValueAssigner()
56 LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty, in assignArg()
181 bool IsRet; member
187 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet, in RISCVIncomingValueAssigner()
190 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet), in RISCVIncomingValueAssigner()
205 LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty, in assignArg()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 901 bool IsFixed, bool IsRet, Type *OrigTy,
907 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
911 bool IsRet, CallLoweringInfo *CLI,
1104 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
1110 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
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| H A D | RISCVISelLowering.cpp | 18997 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, in CC_RISCV() argument
19014 if (!LocVT.isVector() && IsRet && ValNo > 1) in CC_RISCV()
19173 if (IsRet) in CC_RISCV()
19248 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
19254 if (IsRet) { in analyzeInputArgs()
19268 if (IsRet) in analyzeInputArgs()
19275 ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this, in analyzeInputArgs()
19286 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
19291 if (IsRet) in analyzeOutputArgs()
19305 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, in analyzeOutputArgs()
[all …]
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 269 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
273 bool IsRet, CallLoweringInfo *CLI,
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| H A D | LoongArchISelLowering.cpp | 4719 CCState &State, bool IsFixed, bool IsRet, in CC_LoongArch() argument
4728 if (IsRet && ValNo > 1) in CC_LoongArch()
4869 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
4875 if (IsRet) in analyzeInputArgs()
4882 CCInfo, /*IsFixed=*/true, IsRet, ArgTy)) { in analyzeInputArgs()
4892 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
4900 CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) { in analyzeOutputArgs()
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