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/src/sys/contrib/device-tree/Bindings/usb/
H A Dlpc32xx-udc.txt8 * USB Device Low Priority Interrupt
9 * USB Device High Priority Interrupt
10 * USB Device DMA Interrupt
11 * External USB Transceiver Interrupt (OTG ATX)
/src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dcsky,mpintc.txt2 C-SKY Multi-processors Interrupt Controller
5 C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
8 Interrupt number definition:
13 Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
H A Dandestech,ativic32.txt1 * Andestech Internal Vector Interrupt Controller
3 The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
5 bigger External Vector Interrupt Controller.
H A Dti,sci-inta.txt1 Texas Instruments K3 Interrupt Aggregator
4 The Interrupt Aggregator (INTA) provides a centralized machine
10 Interrupt Aggregator
38 TISCI Interrupt Aggregator Node:
46 - ti,sci-dev-id: TISCI device ID of the Interrupt Aggregator.
H A Dimg,pdc-intc.txt1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
30 * Interrupt Specifier Definition
32 Interrupt specifiers consists of 2 cells encoded as follows:
88 // Interrupt source Peripheral 0
102 // Interrupt source SysWake 0 that is active-low level-sensitive
H A Dti,sci-intr.txt1 Texas Instruments K3 Interrupt Router
4 The Interrupt Router (INTR) module provides a mechanism to mux M
6 to be driven per N output. An Interrupt Router can either handle edge triggered
9 Interrupt Router
38 TISCI Interrupt Router Node:
H A Dti,c64x+megamod-pic.txt1 C6X Interrupt Chips
4 * C64X+ Core Interrupt Controller
16 Interrupt Specifier Definition
31 * C64x+ Megamodule Interrupt Controller
65 Interrupt Specifier Definition
H A Dcdns,xtensa-mx.txt1 * Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)
H A Dintel,ce4100-ioapic.txt1 Interrupt chips
4 * Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
H A Darm,vic.txt1 * ARM Vectored Interrupt Controller
3 One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
H A Dti,cp-intc.txt1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
H A Dmrvl,intc.txt1 * Marvell MMP Interrupt controller
46 * Marvell Orion Interrupt controller
53 - reg : Interrupt mask address. A list of 4 byte ranges, one per controller.
H A Dimg,meta-intc.txt28 * Interrupt Specifier Definition
30 Interrupt specifiers consists of 2 cells encoded as follows:
75 // Interrupt source '5' that is level-sensitive.
H A Damazon,al-fic.txt1 Amazon's Annapurna Labs Fabric Interrupt Controller
16 Interrupt Controllers bindings used by client devices.
H A Dmarvell,sei.txt1 Marvell SEI (System Error Interrupt) Controller
4 Marvell SEI (System Error Interrupt) controller is an interrupt
H A Drenesas,rza1-irqc.txt1 DT bindings for the Renesas RZ/A1 Interrupt Controller
3 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
H A Dqca,ath79-misc-intc.txt10 - interrupts: Interrupt specifier for the controllers interrupt.
19 Interrupt Controllers bindings used by client devices.
/src/sys/contrib/device-tree/Bindings/net/
H A Ddavinci_emac.txt15 4 sources: <Receive Threshold Interrupt
16 Receive Interrupt
17 Transmit Interrupt
18 Miscellaneous Interrupt>
/src/sys/contrib/device-tree/Bindings/crypto/
H A Dhisilicon,hip07-sec.txt13 - interrupts: Interrupt specifiers.
16 Interrupt 0 is for the SEC unit error queue.
17 Interrupt 2N + 1 is the completion interrupt for queue N.
18 Interrupt 2N + 2 is the error interrupt for queue N.
/src/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,arc-timer.txt1 Synopsys ARC Local Timer with Interrupt Capabilities
11 - interrupts : single Interrupt going into parent intc
/src/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-ath79.txt15 - interrupts: Interrupt specifier for the controllers interrupt.
21 Interrupt Controllers bindings used by client devices.
/src/sys/contrib/device-tree/Bindings/input/
H A Dti,palmas-pwrbutton.txt7 This module provides a simple power button event via an Interrupt.
12 - interrupts: Interrupt number of power button submodule on device.
/src/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
12 - reg: the register range of the MSCM Interrupt Router
/src/sys/contrib/device-tree/Bindings/slimbus/
H A Dslim-qcom-ctrl.txt17 - interrupts : Interrupt number used by this controller
21 "core" : Interrupt for controller core's BAM
/src/sys/contrib/device-tree/Bindings/iommu/
H A Drockchip,iommu.txt11 - interrupts : Interrupt specifier for the IOMMU instance
12 - interrupt-names : Interrupt name for the IOMMU instance

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