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Searched refs:InstrPtr (Results 1 – 2 of 2) sorted by relevance

/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCombiner.cpp215 for (auto *InstrPtr : InsInstrs) { // for each Use in getDepth() local
217 for (const MachineOperand &MO : InstrPtr->all_uses()) { in getDepth()
235 InstrPtr->findRegisterUseOperandIdx(MO.getReg(), /*TRI=*/nullptr); in getDepth()
237 InstrPtr, UseIdx); in getDepth()
249 InstrPtr, in getDepth()
250 InstrPtr->findRegisterUseOperandIdx(MO.getReg(), in getDepth()
419 for (auto *InstrPtr : Instrs) { in instr2instrSC() local
420 unsigned Opc = InstrPtr->getOpcode(); in instr2instrSC()
500 for (auto *InstrPtr : InsInstrs) in insertDeleteInstructions() local
501 MBB->insert((MachineBasicBlock::iterator)&MI, InstrPtr); in insertDeleteInstructions()
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/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.cpp971 const MachineInstr *InstrPtr = &MI; in addInstrRequirements() local
974 InstrPtr = MRI.getVRegDef(MI.getOperand(3).getReg()); in addInstrRequirements()
975 assert(InstrPtr && "Unexpected type instruction for OpAtomicStore"); in addInstrRequirements()
977 assert(InstrPtr->getOperand(1).isReg() && "Unexpected operand in atomic"); in addInstrRequirements()
978 Register TypeReg = InstrPtr->getOperand(1).getReg(); in addInstrRequirements()