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/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
47 field bits<16> Inst;
61 bits<16> Inst;
63 let Inst{15-10} = 0x01;
64 let Inst{9-7} = rd;
65 let Inst{6-4} = rt;
66 let Inst{3-1} = rs;
67 let Inst{0} = funct;
75 bits<16> Inst;
77 let Inst{15-10} = funct;
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H A DMicroMips32r6InstrFormats.td40 bits<16> Inst;
42 let Inst{15-10} = 0x33;
43 let Inst{9-0} = offset;
50 bits<16> Inst;
52 let Inst{15-10} = op;
53 let Inst{9-7} = rs;
54 let Inst{6-0} = offset;
60 bits<16> Inst;
62 let Inst{15-10} = 0x11;
63 let Inst{9-5} = rs;
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H A DMipsInstrFormats.td74 field bits<32> Inst;
84 let Inst{31-26} = Opcode;
164 let Inst{25-21} = rs;
165 let Inst{20-16} = rt;
166 let Inst{15-11} = rd;
167 let Inst{10-6} = shamt;
168 let Inst{5-0} = funct;
179 bits<32> Inst;
181 let Inst{31-26} = op;
182 let Inst{25-0} = target;
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H A DMipsMSAInstrFormats.td12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
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H A DMicroMipsDSPInstrFormats.td29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
40 let Inst{31-26} = 0b000000;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
44 let Inst{5-0} = 0b111100;
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H A DMips32r6InstrFormats.td182 bits<32> Inst;
184 let Inst{31-26} = OPGROUP_AUI.Value;
185 let Inst{25-21} = rs;
186 let Inst{20-16} = rt;
187 let Inst{15-0} = imm;
191 let Inst{31-26} = OPGROUP_DAUI.Value;
197 bits<32> Inst;
199 let Inst{31-26} = OPGROUP_REGIMM.Value;
200 let Inst{25-21} = 0b00000;
201 let Inst{20-16} = OPCODE5_BGEZAL.Value;
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H A DMipsDSPInstrFormats.td72 let Inst{25-21} = rs;
73 let Inst{20-16} = rt;
74 let Inst{15-11} = rd;
75 let Inst{10-6} = op;
76 let Inst{5-0} = 0b010000;
85 let Inst{25-21} = rs;
86 let Inst{20-16} = 0;
87 let Inst{15-11} = rd;
88 let Inst{10-6} = op;
89 let Inst{5-0} = 0b010000;
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/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td13 let Inst{12-8} = Vu32{4-0};
15 let Inst{20-16} = Rt32{4-0};
17 let Inst{4-0} = Vdd32{4-0};
21 let Inst{11-5} = Ii{6-0};
23 let Inst{20-16} = Rs32{4-0};
25 let Inst{1-0} = Pd4{1-0};
29 let Inst{20-16} = Rss32{4-0};
31 let Inst{12-8} = Rt32{4-0};
33 let Inst{1-0} = Pd4{1-0};
37 let Inst{21-20} = Ii{10-9};
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/src/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp74 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
78 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
82 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
86 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
90 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
94 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
98 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
102 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
106 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
110 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
31 let Inst{15-12} = funct4;
32 let Inst{11-7} = rs1;
33 let Inst{6-2} = rs2;
34 let Inst{1-0} = opcode;
38 // is responsible for setting the appropriate bits in the Inst field.
39 // The bits Inst{6-2} must be set for each instruction.
46 let Inst{15-13} = funct3;
47 let Inst{12} = imm{5};
48 let Inst{11-7} = rd;
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H A DRISCVInstrFormatsV.td63 let Inst{31} = 1;
64 let Inst{30} = 1;
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
80 let Inst{31} = 0;
81 let Inst{30-20} = vtypei;
82 let Inst{19-15} = rs1;
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td15 field bits<32> Inst;
22 let Inst{0-5} = opcode;
92 field bits<64> Inst;
99 let Inst{0-5} = opcode1;
100 let Inst{32-37} = opcode2;
135 let Inst{6-29} = LI;
136 let Inst{30} = aa;
137 let Inst{31} = lk;
151 let Inst{6-10} = BIBO{4-0};
152 let Inst{11-15} = BI;
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/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td13 let Inst{15} = 0;
14 let Inst{14 - 10} = sop;
15 let Inst{9 - 0} = offset;
22 let Inst{15} = 0;
23 let Inst{14 - 10} = sop;
24 let Inst{9 - 0} = offset;
33 let Inst{15 - 11} = 0b01011;
34 let Inst{10 - 8} = rx;
35 let Inst{7 - 5} = rz;
36 let Inst{4 - 2} = ry;
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H A DCSKYInstrFormats.td45 field bits<32> Inst;
46 let Inst{31 - 26} = opcode;
51 field bits<16> Inst;
61 let Inst{25 - 0} = offset;
72 let Inst{25 - 21} = rz;
73 let Inst{20 - 18} = sop;
74 let Inst{17 - 0} = offset;
86 let Inst{25 - 21} = rz;
87 let Inst{20 - 16} = rx;
88 let Inst{15 - 0} = imm16;
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/src/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
93 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
97 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR32BitRegisterClass() argument
100 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); in DecodeGR32BitRegisterClass()
103 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGRH32BitRegisterClass() argument
106 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); in DecodeGRH32BitRegisterClass()
109 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR64BitRegisterClass() argument
112 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); in DecodeGR64BitRegisterClass()
115 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR128BitRegisterClass() argument
118 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); in DecodeGR128BitRegisterClass()
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp42 static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
46 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
48 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
51 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
59 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
62 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
66 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
69 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
72 static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td27 let Inst{31-0} = op;
28 let Inst{17-5} = imm13;
29 let Inst{4-0} = xd;
40 let Inst{31-0} = op;
41 let Inst{9-5} = xj;
42 let Inst{4-0} = xd;
52 let Inst{31-0} = op;
53 let Inst{9-5} = rj;
54 let Inst{4-0} = xd;
64 let Inst{31-0} = op;
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H A DLoongArchLSXInstrFormats.td27 let Inst{31-0} = op;
28 let Inst{17-5} = imm13;
29 let Inst{4-0} = vd;
40 let Inst{31-0} = op;
41 let Inst{9-5} = vj;
42 let Inst{4-0} = vd;
52 let Inst{31-0} = op;
53 let Inst{9-5} = rj;
54 let Inst{4-0} = vd;
64 let Inst{31-0} = op;
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H A DLoongArchInstrFormats.td22 field bits<32> Inst;
57 let Inst{31-0} = op;
58 let Inst{9-5} = rj;
59 let Inst{4-0} = rd;
71 let Inst{31-0} = op;
72 let Inst{14-10} = rk;
73 let Inst{9-5} = rj;
74 let Inst{4-0} = rd;
87 let Inst{31-0} = op;
88 let Inst{16-15} = imm2;
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, in decodeCondBrTarget() argument
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, in decodeDirectBrTarget() argument
76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
88 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
92 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRRCRegisterClass() argument
95 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
98 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRBITRCRegisterClass() argument
101 return decodeRegisterClass(Inst, RegNo, CRBITRegs); in DecodeCRBITRCRegisterClass()
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/src/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp176 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
182 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
185 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
189 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
192 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
195 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
199 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
201 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
205 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td32 field bits<24> Inst;
40 field bits<16> Inst;
52 let Inst{23-20} = op2;
53 let Inst{19-16} = op1;
54 let Inst{15-12} = r;
55 let Inst{11-8} = s;
56 let Inst{7-4} = t;
57 let Inst{3-0} = op0;
68 let Inst{23-20} = imm4;
69 let Inst{19-16} = op1;
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp75 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); in createRISCVMCAsmInfo() local
76 MAI->addInitialFrameState(Inst); in createRISCVMCAsmInfo()
169 void updateState(const MCInst &Inst, uint64_t Addr) override { in updateState() argument
175 if (isTerminator(Inst) || isCall(Inst)) { in updateState()
180 switch (Inst.getOpcode()) { in updateState()
184 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs(); in updateState()
186 auto DefReg = Inst.getOperand(I).getReg(); in updateState()
193 setGPRState(Inst.getOperand(0).getReg(), in updateState()
194 Addr + (Inst.getOperand(1).getImm() << 12)); in updateState()
199 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, in evaluateBranch() argument
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/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td14 field bits<64> Inst;
145 // A - Inst[5-0] = A[5-0], when the format has A. A is always a register.
146 // B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
160 let Inst{31-27} = major;
161 let Inst{16} = b16;
162 let Inst{5} = N;
170 let Inst{26-18} = S21{10-2};
171 let Inst{15-6} = S21{20-11};
172 let Inst{4-0} = cc;
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/src/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp70 static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, in DecodeGPR8RegisterClass() argument
77 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
81 static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, in DecodeLD8RegisterClass() argument
88 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
92 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
95 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
98 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
101 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
105 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
108 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
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