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Searched refs:Imm (Results 1 – 25 of 378) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
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/src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
99 return ShOp | (Imm << 3); in getSORegOpc()
106 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } in getSOImmValImm() argument
109 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } in getSOImmValRot() argument
115 inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
118 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
121 unsigned TZ = llvm::countr_zero(Imm); in getSOImmValRotate()
128 if ((llvm::rotr<uint32_t>(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
133 if (Imm & 63U) { in getSOImmValRotate()
134 unsigned TZ2 = llvm::countr_zero(Imm & ~63U); in getSOImmValRotate()
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/src/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp106 static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, in decodeCallOperand() argument
108 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeCallOperand()
109 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2))); in decodeCallOperand()
113 static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, in decodeJumpOperand() argument
115 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeJumpOperand()
116 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
120 static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, in decodeBranchOperand() argument
127 assert(isUInt<12>(Imm) && "Invalid immediate"); in decodeBranchOperand()
128 if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true, in decodeBranchOperand()
130 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeBranchOperand()
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/src/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp182 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
183 if (!isUInt<N>(Imm)) in decodeUImmOperand()
185 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
190 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
191 if (!isUInt<N>(Imm)) in decodeSImmOperand()
193 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
197 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
200 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
203 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU2ImmOperand() argument
206 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp67 int64_t Imm = Op.getImm(); in printU16ImmOperand() local
68 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
69 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
105 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
106 if (Imm != 0) { in printOffset()
113 O << formatDec(SignExtend32<24>(Imm)); in printOffset()
122 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printFlatOffset() local
123 if (Imm != 0) { in printFlatOffset()
132 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI))); in printFlatOffset()
183 auto Imm = MI->getOperand(OpNo).getImm(); in printCPol() local
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/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
46 unsigned Shamt = llvm::countr_zero(Imm); in GetInstSeqLsSLL()
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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H A DMipsISelDAGToDAG.h93 virtual bool selectVSplat(SDNode *N, APInt &Imm,
96 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
98 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
100 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
102 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
104 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
106 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
108 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
110 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
112 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
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H A DMipsSEISelDAGToDAG.h94 bool selectVSplat(SDNode *N, APInt &Imm,
97 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
100 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
102 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
104 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
106 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
108 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
110 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
112 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
114 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
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H A DMipsISelDAGToDAG.cpp157 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, in selectVSplat() argument
163 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1()
168 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2()
173 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3()
178 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4()
183 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5()
188 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6()
193 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8()
198 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5()
203 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2()
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/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaOperands.td26 def imm8 : Immediate<i32, [{ return Imm >= -128 && Imm <= 127; }], "Imm8_AsmOperand"> {
34 def imm8_sh8 : Immediate<i32, [{ return Imm >= -32768 && Imm <= 32512 && ((Imm & 0xFF) == 0); }],
42 def imm12 : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12_AsmOperand"> {
49 def imm12m : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12m_AsmOperand"> {
56 def uimm4 : Immediate<i32, [{ return Imm >= 0 && Imm <= 15; }], "Uimm4_AsmOperand"> {
63 def uimm5 : Immediate<i32, [{ return Imm >= 0 && Imm <= 31; }], "Uimm5_AsmOperand"> {
70 def imm1_16 : Immediate<i32, [{ return Imm >= 1 && Imm <= 16; }], "Imm1_16_AsmOperand"> {
77 def shimm1_31 : Immediate<i32, [{ return Imm >= 1 && Imm <= 31; }], "Shimm1_31_AsmOperand"> {
85 [{ return Imm >= 0 && Imm <= 255; }],
91 [{ return Imm >= 0 && Imm <= 510 && (Imm & 0x1 == 0); }],
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp22 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { in getChunk() argument
25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; in getChunk()
124 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { in updateImm() argument
129 Imm &= ~(Mask << (Idx * 16)); in updateImm()
132 Imm |= Mask << (Idx * 16); in updateImm()
134 return Imm; in updateImm()
373 static bool tryEorOfLogicalImmediates(uint64_t Imm, in tryEorOfLogicalImmediates() argument
383 if ((Imm & Mask) != ((Imm >> BigSize) & Mask)) { in tryEorOfLogicalImmediates()
394 uint64_t RunStarts = Imm & ~rotl<uint64_t>(Imm, 1); in tryEorOfLogicalImmediates()
436 uint64_t RotatedImm = rotr<uint64_t>(Imm, Rotation); in tryEorOfLogicalImmediates()
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp123 unsigned Imm = MI->getOperand(OpNo).getImm(); in printCSRSystemRegister() local
124 auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm); in printCSRSystemRegister()
131 markup(O, Markup::Register) << formatImm(Imm); in printCSRSystemRegister()
177 unsigned Imm = MI->getOperand(OpNo).getImm(); in printFPImmOperand() local
178 if (Imm == 1) { in printFPImmOperand()
180 } else if (Imm == 30) { in printFPImmOperand()
182 } else if (Imm == 31) { in printFPImmOperand()
185 float FPVal = RISCVLoadFPImm::getFPImm(Imm); in printFPImmOperand()
210 unsigned Imm = MI->getOperand(OpNo).getImm(); in printVTypeI() local
213 if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED || in printVTypeI()
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H A DRISCVBaseInfo.cpp182 APInt Imm = FPImm.bitcastToAPInt(); in getLoadFPImm() local
184 if (Imm.extractBitsAsZExtValue(21, 0) != 0) in getLoadFPImm()
187 bool Sign = Imm.extractBitsAsZExtValue(1, 31); in getLoadFPImm()
188 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21); in getLoadFPImm()
189 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23); in getLoadFPImm()
209 float RISCVLoadFPImm::getFPImm(unsigned Imm) { in getFPImm() argument
210 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate"); in getFPImm()
214 if (Imm == 0) { in getFPImm()
216 Imm = 16; in getFPImm()
219 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first; in getFPImm()
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/src/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp98 int64_t Imm = MO.getImm(); in printCvtMode() local
102 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
106 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
110 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG) in printCvtMode()
114 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
155 int64_t Imm = MO.getImm(); in printCmpMode() local
159 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode()
162 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { in printCmpMode()
229 int Imm = (int) MO.getImm(); in printLdStCode() local
231 if (Imm) in printLdStCode()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMIRFormatter.cpp21 std::optional<unsigned int> OpIdx, int64_t Imm) const { in printImm()
26 printSDelayAluImm(Imm, OS); in printImm()
29 MIRFormatter::printImm(OS, MI, OpIdx, Imm); in printImm()
38 StringRef Src, int64_t &Imm, in parseImmMnemonic() argument
44 return parseSDelayAluImmMnemonic(OpIdx, Imm, Src, ErrorCallback); in parseImmMnemonic()
51 void AMDGPUMIRFormatter::printSDelayAluImm(int64_t Imm, in printSDelayAluImm() argument
59 uint64_t Id0 = (Imm & 0xF); in printSDelayAluImm()
60 uint64_t Skip = ((Imm >> 4) & 0x7); in printSDelayAluImm()
61 uint64_t Id1 = ((Imm >> 7) & 0xF); in printSDelayAluImm()
95 const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src, in parseSDelayAluImmMnemonic() argument
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/src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
55 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
58 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
61 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
65 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
69 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
73 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
80 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
104 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
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H A DX86ShuffleDecode.cpp26 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeINSERTPSMask() argument
34 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
35 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
36 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
99 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm, in DecodePSLLDQMask() argument
106 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask()
111 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm, in DecodePSRLDQMask() argument
117 unsigned Base = i + Imm; in DecodePSRLDQMask()
124 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm, in DecodePALIGNRMask() argument
130 unsigned Base = i + Imm; in DecodePALIGNRMask()
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/src/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp227 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
230 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
231 Inst.addOperand(MCOperand::createImm(Imm << S)); in decodeUImmOperand()
236 static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm, in decodeOImmOperand() argument
239 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeOImmOperand()
240 Inst.addOperand(MCOperand::createImm(Imm + 1)); in decodeOImmOperand()
244 static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address, in decodeLRW16Imm8() argument
246 assert(isUInt<8>(Imm) && "Invalid immediate"); in decodeLRW16Imm8()
247 if ((Imm >> 7) & 0x1) { in decodeLRW16Imm8()
248 Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2)); in decodeLRW16Imm8()
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, in decodeCondBrTarget() argument
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, in decodeDirectBrTarget() argument
75 int32_t Offset = SignExtend32<24>(Imm); in decodeDirectBrTarget()
248 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, in decodeUImmOperand() argument
251 if (!isUInt<N>(Imm)) in decodeUImmOperand()
253 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
258 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, in decodeSImmOperand() argument
261 if (!isUInt<N>(Imm)) in decodeSImmOperand()
263 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp398 ImmOp Imm; member
421 Imm = o.Imm; in RISCVOperand()
491 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, in evaluateConstantImm()
495 return RE->evaluateAsConstant(Imm); in evaluateConstantImm()
500 Imm = CE->getValue(); in evaluateConstantImm()
510 int64_t Imm; in isBareSimmNLsb0() local
514 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); in isBareSimmNLsb0()
519 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
526 int64_t Imm; in isBareSymbol() local
529 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isBareSymbol()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp104 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, in decodeSOPPBrTarget() argument
111 APInt SignedOffset(18, Imm * 4, true); in decodeSOPPBrTarget()
116 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSOPPBrTarget()
119 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, in decodeSMEMOffset() argument
124 Offset = SignExtend64<24>(Imm); in decodeSMEMOffset()
126 Offset = Imm & 0xFFFFF; in decodeSMEMOffset()
128 Offset = SignExtend64<21>(Imm); in decodeSMEMOffset()
153 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
157 return addOperand(Inst, DAsm->DecoderName(Imm)); \
164 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
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/src/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp81 auto Imm = OffsetOp.getImm(); in printMemOperand() local
82 if (Imm >= 0) in printMemOperand()
83 O << " + " << formatImm(Imm); in printMemOperand()
85 O << " - " << formatImm(-Imm); in printMemOperand()
107 int32_t Imm = Op.getImm(); in printBrTargetOperand() local
108 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); in printBrTargetOperand()
110 int16_t Imm = Op.getImm(); in printBrTargetOperand() local
111 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); in printBrTargetOperand()
/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h52 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, in getIntImmCost() argument
65 if (Imm == 0) in getIntImmCost()
67 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
69 if (isInt<21>(Imm.getZExtValue())) in getIntImmCost()
71 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
72 if ((Imm.getSExtValue() & 0xFFFF) == 0) in getIntImmCost()
81 const APInt &Imm, Type *Ty,
84 return getIntImmCost(Imm, Ty, CostKind);
88 const APInt &Imm, Type *Ty, in getIntImmCostIntrin() argument
90 return getIntImmCost(Imm, Ty, CostKind); in getIntImmCostIntrin()
/src/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_hexagon.cpp43 encodeExtendedTransferImmediate(uint32_t Imm, RegNum DestReg, in encodeExtendedTransferImmediate() argument
49 Imm = Imm & 0x03f; in encodeExtendedTransferImmediate()
52 return PO_TFR_IMM | ParseBits | (Imm << 5) | (DestReg & REG_MASK); in encodeExtendedTransferImmediate()
56 encodeConstantExtender(uint32_t Imm) XRAY_NEVER_INSTRUMENT { in encodeConstantExtender() argument
68 Imm = Imm >> 6; in encodeConstantExtender()
70 const uint32_t high = (Imm & IMM_MASK_HIGH) << 16; in encodeConstantExtender()
71 const uint32_t low = Imm & IMM_MASK_LOW; in encodeConstantExtender()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp66 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
69 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
72 static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
75 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
78 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
81 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
84 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
144 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
147 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
150 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
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