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Searched refs:ISA (Results 1 – 25 of 175) sorted by relevance

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/src/contrib/libdivsufsort/lib/
H A Dtrsort.c264 tr_copy(saidx_t *ISA, const saidx_t *SA, in tr_copy() argument
274 if((0 <= (s = *c - depth)) && (ISA[s] == v)) { in tr_copy()
276 ISA[s] = d - SA; in tr_copy()
280 if((0 <= (s = *c - depth)) && (ISA[s] == v)) { in tr_copy()
282 ISA[s] = d - SA; in tr_copy()
289 tr_partialcopy(saidx_t *ISA, const saidx_t *SA, in tr_partialcopy() argument
299 if((0 <= (s = *c - depth)) && (ISA[s] == v)) { in tr_partialcopy()
301 rank = ISA[s + depth]; in tr_partialcopy()
303 ISA[s] = newrank; in tr_partialcopy()
309 rank = ISA[*e]; in tr_partialcopy()
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/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68k.td23 "Is M68000 ISA supported">;
27 "Is M68010 ISA supported",
32 "Is M68020 ISA supported",
37 "Is M68030 ISA supported",
42 "Is M68881 (FPU) ISA supported">;
46 "Is M68882 (FPU) ISA supported",
51 "Is M68040 ISA supported",
56 "Is M68060 ISA supported",
/src/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DPPCTargetParser.def116 PPC_LNX_FEATURE("arch_2_05","CPU supports ISA 205 (eg, POWER6)",PPCF_ARCH205,0x00001000,PPC_FAWORD_…
117 PPC_LNX_FEATURE("arch_2_06","CPU supports ISA 206 (eg, POWER7)",PPCF_ARCH206,0x00000100,PPC_FAWORD_…
118 PPC_LNX_FEATURE("arch_2_07","CPU supports ISA 207 (eg, POWER8)",PPCF_ARCH207,0x80000000,PPC_FAWORD_…
119 PPC_LNX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",PPCF_ARCH30,0x00800000,PPC_FAWORD_HW…
120 PPC_LNX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",PPCF_ARCH31,0x00040000,PPC_FAWORD_HW…
122 PPC_LNX_FEATURE("booke","CPU supports the Embedded ISA category",PPCF_BOOKE,0x00008000,PPC_FAWORD_H…
140 PPC_LNX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE ISA",PPCF_PA6T,0x00000800,PPC_FAWORD_HWCAP)
141 PPC_LNX_FEATURE("power4","CPU supports ISA 200 (eg, POWER4)",PPCF_POWER4,0x00080000,PPC_FAWORD_HWCA…
142 PPC_LNX_FEATURE("power5","CPU supports ISA 202 (eg, POWER5)",PPCF_POWER5,0x00040000,PPC_FAWORD_HWCA…
143 PPC_LNX_FEATURE("power5+","CPU supports ISA 203 (eg, POWER5+)",PPCF_POWER5P,0x00020000,PPC_FAWORD_H…
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/src/contrib/llvm-project/llvm/lib/IR/
H A DVFABIDemangler.cpp35 static ParseRet tryParseISA(StringRef &MangledName, VFISAKind &ISA) { in tryParseISA() argument
40 ISA = VFISAKind::LLVM; in tryParseISA()
42 ISA = StringSwitch<VFISAKind>(MangledName.take_front(1)) in tryParseISA()
78 static ParseRet tryParseVLEN(StringRef &ParseString, VFISAKind ISA, in tryParseVLEN() argument
82 if (ISA != VFISAKind::SVE) { in tryParseVLEN()
302 static std::optional<ElementCount> getElementCountForTy(const VFISAKind ISA, in getElementCountForTy() argument
305 assert(ISA == VFISAKind::SVE && in getElementCountForTy()
323 getScalableECFromSignature(const FunctionType *Signature, const VFISAKind ISA, in getScalableECFromSignature() argument
334 std::optional<ElementCount> EC = getElementCountForTy(ISA, PTy); in getScalableECFromSignature()
349 std::optional<ElementCount> ReturnEC = getElementCountForTy(ISA, RetTy); in getScalableECFromSignature()
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/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips.td32 // Predicates for the instruction group membership such as ISA's.
84 "Mips I ISA Support [highly experimental]">;
86 "Mips II ISA Support [highly experimental]",
95 "MIPS III ISA Support [highly experimental]",
106 "Mips4", "MIPS IV ISA Support",
113 "MIPS V ISA Support [highly experimental]",
116 "Mips32 ISA Support",
120 "Mips32r2", "Mips32r2 ISA Support",
124 "Mips32r3", "Mips32r3 ISA Support",
127 "Mips32r5", "Mips32r5 ISA Support",
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/src/sys/contrib/device-tree/Bindings/arm/hisilicon/
H A Dhisilicon-low-pin-count.txt3 provides I/O access to some legacy ISA devices.
12 - #address-cells: must be 2 which stick to the ISA/EISA binding doc.
13 - #size-cells: must be 1 which stick to the ISA/EISA binding doc.
18 ISA/EISA binding specification.
/src/crypto/openssl/doc/man3/
H A DOPENSSL_ppccap.pod53 capability gates the use of later ISA vector instructions. The associated probe
57 at specific ISA levels. However, disabling this capability disables a subset of
58 vector extensions added at specific ISA levels even if they are otherwise
65 Meaning: Use instructions added in ISA level 2.07. The associated probe
68 Effect: Enables AES, SHA-2 sigma, and other ISA 2.07 instructions for AES, SHA-2,
85 Meaning: Use instructions added in ISA level 3.00. The associated probe
88 Effect: Enables use of the polynomial multiply and other ISA 3.00 instructions
117 Meaning: Use instructions added in ISA level 3.1. The associated probe instruction
120 Effect: Enables use of ISA 3.1 instructions in ChaCha20.
/src/sys/contrib/zstd/lib/dictBuilder/
H A Ddivsufsort.c1112 tr_copy(int *ISA, const int *SA, in tr_copy() argument
1122 if((0 <= (s = *c - depth)) && (ISA[s] == v)) { in tr_copy()
1124 ISA[s] = d - SA; in tr_copy()
1128 if((0 <= (s = *c - depth)) && (ISA[s] == v)) { in tr_copy()
1130 ISA[s] = d - SA; in tr_copy()
1137 tr_partialcopy(int *ISA, const int *SA, in tr_partialcopy() argument
1147 if((0 <= (s = *c - depth)) && (ISA[s] == v)) { in tr_partialcopy()
1149 rank = ISA[s + depth]; in tr_partialcopy()
1151 ISA[s] = newrank; in tr_partialcopy()
1157 rank = ISA[*e]; in tr_partialcopy()
[all …]
/src/crypto/openssl/Configurations/platform/Windows/
H A Dcppbuilder.pm3 use vars qw(@ISA);
6 @ISA = qw(platform::Windows::MSVC);
H A DMSVC.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::Windows);
/src/crypto/openssl/Configurations/
H A Dplatform.pm5 use vars qw(@ISA);
14 @ISA = ("platform::$module");
/src/crypto/openssl/util/perl/OpenSSL/
H A DGlob.pm9 use vars qw($VERSION @ISA @EXPORT);
12 @ISA = qw(Exporter);
/src/crypto/openssl/Configurations/platform/
H A DCygwin.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::mingw);
H A DAIX.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::Unix);
H A Dmingw.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::Unix);
H A DWindows.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::BASE);
H A DVMS.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::BASE);
H A DUnix.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::BASE);
/src/crypto/openssl/util/perl/OpenSSL/Test/
H A DSimple.pm14 use vars qw($VERSION @ISA @EXPORT @EXPORT_OK %EXPORT_TAGS);
16 @ISA = qw(Exporter);
H A DUtils.pm14 use vars qw($VERSION @ISA @EXPORT @EXPORT_OK %EXPORT_TAGS);
16 @ISA = qw(Exporter);
/src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
29 RISC-V supervisor ISA manual, with only the following three interrupts being
/src/crypto/openssl/external/perl/Text-Template-1.56/t/
H A Dstrict.t12 @Emptyclass1::ISA = 'Text::Template';
13 @Emptyclass2::ISA = 'Text::Template';
H A Dprepend.t12 @Emptyclass1::ISA = 'Text::Template';
13 @Emptyclass2::ISA = 'Text::Template';
/src/crypto/krb5/src/util/
H A Dt_template.pm4 use vars qw(@ISA @EXPORT_OK);
6 @ISA=();
/src/crypto/openssl/util/perl/OpenSSL/Util/
H A DPod.pm14 use vars qw($VERSION @ISA @EXPORT @EXPORT_OK %EXPORT_TAGS);
16 @ISA = qw(Exporter);

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