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Searched refs:IO_ICU1 (Results 1 – 6 of 6) sorted by relevance

/src/sys/x86/x86/
H A Dintr_machdep.c520 outb(IO_ICU1, ICW1_RESET | ICW1_IC4); in atpic_reset()
521 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS); in atpic_reset()
522 outb(IO_ICU1 + ICU_IMR_OFFSET, IRQ_MASK(ICU_SLAVEID)); in atpic_reset()
523 outb(IO_ICU1 + ICU_IMR_OFFSET, MASTER_MODE); in atpic_reset()
524 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); in atpic_reset()
525 outb(IO_ICU1, OCW3_SEL | OCW3_RR); in atpic_reset()
/src/sys/amd64/vmm/
H A Dvmm_ioport.c52 [IO_ICU1] = vatpic_master_handler,
53 [IO_ICU1 + ICU_IMR_OFFSET] = vatpic_master_handler,
/src/sys/isa/
H A Disareg.h47 #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ macro
/src/usr.sbin/bhyve/amd64/
H A Dpci_lpc.c55 #define IO_ICU1 0x20 macro
342 dsdt_fixed_ioport(IO_ICU1, 2); in pci_lpc_write_dsdt()
/src/sys/powerpc/mpc85xx/
H A Datpic.c153 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2); in atpic_isa_identify()
/src/sys/x86/isa/
H A Datpic.c156 ATPIC(IO_ICU1, 0, atpic_eoi_master),