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Searched refs:HasDisjunctSubRegs (Results 1 – 7 of 7) sorted by relevance

/src/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp165 HasDisjunctSubRegs(false), Constant(R->getValueAsBit("isConstant")), in CodeGenRegister()
282 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1; in computeSubRegs()
306 HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs; in computeSubRegs()
2218 RC.HasDisjunctSubRegs = false; in computeDerivedInfo()
2221 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
H A DCodeGenRegisters.h179 bool HasDisjunctSubRegs = false; variable
361 bool HasDisjunctSubRegs; variable
/src/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1413 << (RC.HasDisjunctSubRegs ? "true" : "false") in runTargetDesc()
1841 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1886 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h66 const bool HasDisjunctSubRegs; variable
H A DMachineRegisterInfo.h228 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; in shouldTrackSubRegLiveness()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp382 if (!RC.HasDisjunctSubRegs) in getLaneMaskForMO()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1432 if (RegClass->HasDisjunctSubRegs) { in canRenameMOP()