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Searched refs:GeneratePressureSet (Results 1 – 5 of 5) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td392 let GeneratePressureSet = 0;
400 let GeneratePressureSet = 0;
410 let GeneratePressureSet = 0;
600 let GeneratePressureSet = 0;
613 let GeneratePressureSet = 0;
634 let GeneratePressureSet = 0;
684 let GeneratePressureSet = 0;
763 let GeneratePressureSet = 0, HasSGPR = 1 in {
803 } // End GeneratePressureSet = 0
813 let GeneratePressureSet = 0 in {
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/src/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp762 GeneratePressureSet = R->getValueAsBit("GeneratePressureSet"); in CodeGenRegisterClass()
849 GeneratePressureSet = false; in CodeGenRegisterClass()
877 GeneratePressureSet |= Super.GeneratePressureSet; in inheritProperties()
2017 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) in computeRegUnitSets()
2134 assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) && in computeRegUnitSets()
H A DCodeGenRegisters.h367 bool GeneratePressureSet; variable
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td599 let GeneratePressureSet = 0;
605 let GeneratePressureSet = 0;
654 // GeneratePressureSet = 0 here is a temporary workaround for lots of
656 let GeneratePressureSet = 0 in {
690 let GeneratePressureSet = 0 in {
/src/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td331 bit GeneratePressureSet = true;