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Searched refs:FPR64 (Results 1 – 25 of 28) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td20 def FADD_D : FP_ALU_3R<0x01010000, FPR64>;
21 def FSUB_D : FP_ALU_3R<0x01030000, FPR64>;
22 def FMUL_D : FP_ALU_3R<0x01050000, FPR64>;
23 def FDIV_D : FP_ALU_3R<0x01070000, FPR64>;
24 def FMADD_D : FP_ALU_4R<0x08200000, FPR64>;
25 def FMSUB_D : FP_ALU_4R<0x08600000, FPR64>;
26 def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>;
27 def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>;
28 def FMAX_D : FP_ALU_3R<0x01090000, FPR64>;
29 def FMIN_D : FP_ALU_3R<0x010b0000, FPR64>;
[all …]
H A DLoongArchFloatInstrFormats.td19 // Some FP instructions are defined twice, for accepting FPR32 and FPR64, but
H A DLoongArchRegisterInfo.td171 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
H A DLoongArchLSXInstrInfo.td1675 def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm),
1676 (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>;
1834 def : Pat<(lsxsplatf64 FPR64:$fj),
1835 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>;
H A DLoongArchLASXInstrInfo.td1555 def : Pat<(vector_insert v4f64:$vd, FPR64:$fj, uimm2:$imm),
1556 (XVINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm2:$imm)>;
1711 def : Pat<(lasxsplatf64 FPR64:$fj),
1712 (XVREPLVE0_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64))>;
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td59 def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
74 def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;
79 def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
173 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
177 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,
185 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
186 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
188 def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
189 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
190 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
[all …]
H A DRISCVInstrInfoZfa.td102 def FLI_D : FPFLI_r<0b1111001, 0b00001, 0b000, FPR64, "fli.d">,
106 def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, Commutable=1>;
107 def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, Commutable=1>;
110 def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,
112 def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">,
117 : FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,
121 def FLTQ_D : FPCmp_rr<0b1010001, 0b101, "fltq.d", FPR64>;
122 def FLEQ_D : FPCmp_rr<0b1010001, 0b100, "fleq.d", FPR64>;
128 def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
130 def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
[all …]
H A DRISCVScheduleXSf.td29 foreach f = ["FPR16", "FPR32", "FPR64"] in {
53 foreach f = ["FPR16", "FPR32", "FPR64"] in {
H A DRISCVInstrInfoC.td508 def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
566 def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
740 def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;
741 def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64:$rs2, SPMem:$rs1, 0)>;
988 def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
989 (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
1030 def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
1031 (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
H A DRISCVInstrInfoZfh.td46 ?, ?, FPR32, FPR64, FPR16>;
48 ?, ?, FPR32, FPR64, FPR16>;
567 def : Pat<(f16 (any_fpround FPR64:$rs1)), (FCVT_H_D FPR64:$rs1, FRM_DYN)>;
571 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR64:$rs2)),
573 def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs2, FRM_RNE))>;
H A DRISCVInstrInfoXTHead.td439 def TH_FLRD : THLoadIndexed<FPR64, 0b01100, "th.flrd">,
441 def TH_FSRD : THStoreIndexed<FPR64, 0b01100, "th.fsrd">,
455 def TH_FLURD : THLoadIndexed<FPR64, 0b01110, "th.flurd">,
457 def TH_FSURD : THStoreIndexed<FPR64, 0b01110, "th.fsurd">,
812 defm : StIdxPat<store, TH_FSRD, FPR64, f64>;
822 defm : StZextIdxPat<store, TH_FSURD, FPR64, f64>;
H A DRISCVInstrInfoXSf.td714 !eq(Sew, 64) : FPR64);
718 !eq(Scalar, f64) : "FPR64");
H A DRISCVRegisterInfo.td275 def FPR64 : RISCVRegisterClass<[f64], 64, (add
H A DRISCVSchedSiFive7.td990 foreach f = ["FPR16", "FPR32", "FPR64"] in {
1006 foreach f = ["FPR16", "FPR32", "FPR64"] in {
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1959 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
1962 (int_aarch64_fjcvtzs FPR64:$Rn))]> {
2243 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
3358 // Match all load 64 bits width whose type is compatible with FPR64
3517 // Match all load 64 bits width whose type is compatible with FPR64
3714 // Match all load 64 bits width whose type is compatible with FPR64
4122 // Match all store 64 bits width whose type is compatible with FPR64
4125 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
4126 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
4127 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
[all …]
H A DAArch64InstrFormats.td4984 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
4985 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
4990 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
4991 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
5035 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
5037 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
5044 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
5046 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
5105 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
5121 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
[all …]
H A DAArch64RegisterInfo.td467 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
475 64, (trunc FPR64, 16)>;
506 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
508 [(rotl FPR64, 0), (rotl FPR64, 1),
509 (rotl FPR64, 2)]>;
511 [(rotl FPR64, 0), (rotl FPR64, 1),
512 (rotl FPR64, 2), (rotl FPR64, 3)]>;
559 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
701 defm VecListOne : VectorList<1, FPR64, FPR128>;
729 def FPR64Op : RegisterOperand<FPR64, "printOperand"> {
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H A DAArch64InstrGISel.td323 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
324 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
325 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
H A DAArch64FrameLowering.cpp2917 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enumerator
2928 case FPR64: in getScale()
2989 RPI.Type = RegPairInfo::FPR64; in computeCalleeSaveRegisterPairs()
3020 case RegPairInfo::FPR64: in computeCalleeSaveRegisterPairs()
3207 case RegPairInfo::FPR64: in spillCalleeSavedRegisters()
3448 case RegPairInfo::FPR64: in restoreCalleeSavedRegisters()
H A DAArch64SVEInstrInfo.td830 def : Pat<(nxv2f64 (splat_vector (f64 FPR64:$src))),
831 (DUP_ZZI_D (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), 0)>;
3174 def : Pat<(nxv2i64 (vector_insert (nxv2i64 (undef)), (i64 FPR64:$src), 0)),
3175 (INSERT_SUBREG (nxv2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
3193 def : Pat<(nxv2f64 (vector_insert (nxv2f64 (undef)), (f64 FPR64:$src), 0)),
3194 (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
3212 def : Pat<(nxv2f64 (vector_insert nxv2f64:$vec, (f64 FPR64:$src), 0)),
3213 (SEL_ZPZZ_D (PTRUE_D 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), ZPR:$vec)>;
3290 def : Pat<(nxv2f64 (vector_insert nxv2f64:$vec, (f64 FPR64:$src), GPR64:$index)),
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td210 class FPR64<bits<16> num, string n, FPR32 high>
217 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
227 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
232 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
237 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
238 !cast<FPR64>("F"#I#"D")>;
252 // A full 128-bit vector register, with an FPR64 as its high part.
253 class VR128<bits<16> num, string n, FPR64 high>
261 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
/src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBanks.td16 def FPRBRegBank : RegisterBank<"FPRB", [FPR64]>;
/src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp322 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; in isFpOrNEON() local
331 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
H A DCSKYInstrInfoF2.td26 let MIOperandInfo = (ops FPR64, uimm5);
30 def FPR64Op : RegisterOperand<FPR64, "printFPR">;

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