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Searched refs:FIFO (Results 1 – 25 of 76) sorted by relevance

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/src/tools/regression/poll/l/
H A Dpipepoll.out10 ok 9 FIFO state 0: expected 0; got 0
11 ok 10 FIFO state 1: expected 0; got 0
12 ok 11 FIFO state 2: expected POLLIN; got POLLIN
13 ok 12 FIFO state 2a: expected 0; got 0
14 ok 13 FIFO state 3: expected POLLHUP; got POLLHUP
15 ok 14 FIFO state 4: expected 0; got 0
16 ok 15 FIFO state 5: expected POLLIN; got POLLIN
17 ok 16 FIFO state 6: expected POLLIN | POLLHUP; got POLLIN | POLLHUP
18 ok 17 FIFO state 6a: expected POLLHUP; got POLLHUP
19 not ok 18 FIFO state 6b: expected POLLHUP; got 0
[all …]
H A Dpipeselect.out10 not ok 9 FIFO state 0: expected set; got clear
11 ok 10 FIFO state 1: expected clear; got clear
12 ok 11 FIFO state 2: expected set; got set
13 ok 12 FIFO state 2a: expected clear; got clear
14 ok 13 FIFO state 3: expected set; got set
15 ok 14 FIFO state 4: expected clear; got clear
16 ok 15 FIFO state 5: expected set; got set
17 ok 16 FIFO state 6: expected set; got set
18 ok 17 FIFO state 6a: expected set; got set
19 not ok 18 FIFO state 6b: expected set; got clear
[all …]
/src/tools/regression/poll/7/
H A Dpipepoll.out10 ok 9 FIFO state 0: expected 0; got 0
11 ok 10 FIFO state 1: expected 0; got 0
12 ok 11 FIFO state 2: expected POLLIN; got POLLIN
13 ok 12 FIFO state 2a: expected 0; got 0
14 not ok 13 FIFO state 3: expected POLLHUP; got 0
15 ok 14 FIFO state 4: expected 0; got 0
16 ok 15 FIFO state 5: expected POLLIN; got POLLIN
17 not ok 16 FIFO state 6: expected POLLIN | POLLHUP; got POLLIN
18 not ok 17 FIFO state 6a: expected POLLHUP; got 0
19 ok 18 FIFO state 6b: expected 0; got 0
[all …]
H A Dpipeselect.out10 ok 9 FIFO state 0: expected clear; got clear
11 ok 10 FIFO state 1: expected clear; got clear
12 ok 11 FIFO state 2: expected set; got set
13 ok 12 FIFO state 2a: expected clear; got clear
14 not ok 13 FIFO state 3: expected set; got clear
15 ok 14 FIFO state 4: expected clear; got clear
16 ok 15 FIFO state 5: expected set; got set
17 ok 16 FIFO state 6: expected set; got set
18 not ok 17 FIFO state 6a: expected set; got clear
19 ok 18 FIFO state 6b: expected clear; got clear
[all …]
/src/tools/regression/poll/m/
H A Dpipepoll.out10 ok 9 FIFO state 0: expected 0; got 0
11 ok 10 FIFO state 1: expected 0; got 0
12 ok 11 FIFO state 2: expected POLLIN; got POLLIN
13 ok 12 FIFO state 2a: expected 0; got 0
14 ok 13 FIFO state 3: expected POLLHUP; got POLLHUP
15 ok 14 FIFO state 4: expected 0; got 0
16 ok 15 FIFO state 5: expected POLLIN; got POLLIN
17 ok 16 FIFO state 6: expected POLLIN | POLLHUP; got POLLIN | POLLHUP
18 ok 17 FIFO state 6a: expected POLLHUP; got POLLHUP
19 ok 18 FIFO state 6b: expected POLLHUP; got POLLHUP
[all …]
H A Dpipeselect.out10 not ok 9 FIFO state 0: expected set; got clear
11 ok 10 FIFO state 1: expected clear; got clear
12 ok 11 FIFO state 2: expected set; got set
13 ok 12 FIFO state 2a: expected clear; got clear
14 ok 13 FIFO state 3: expected set; got set
15 ok 14 FIFO state 4: expected clear; got clear
16 ok 15 FIFO state 5: expected set; got set
17 ok 16 FIFO state 6: expected set; got set
18 ok 17 FIFO state 6a: expected set; got set
19 ok 18 FIFO state 6b: expected set; got set
[all …]
/src/tools/regression/poll/n/
H A Dpipepoll.out10 ok 9 FIFO state 0: expected 0; got 0
11 ok 10 FIFO state 1: expected 0; got 0
12 ok 11 FIFO state 2: expected POLLIN; got POLLIN
13 ok 12 FIFO state 2a: expected 0; got 0
14 ok 13 FIFO state 3: expected POLLHUP; got POLLHUP
15 ok 14 FIFO state 4: expected 0; got 0
16 ok 15 FIFO state 5: expected POLLIN; got POLLIN
17 ok 16 FIFO state 6: expected POLLIN | POLLHUP; got POLLIN | POLLHUP
18 ok 17 FIFO state 6a: expected POLLHUP; got POLLHUP
19 ok 18 FIFO state 6b: expected 0; got 0
[all …]
H A Dpipeselect.out10 ok 9 FIFO state 0: expected clear; got clear
11 ok 10 FIFO state 1: expected clear; got clear
12 ok 11 FIFO state 2: expected set; got set
13 ok 12 FIFO state 2a: expected clear; got clear
14 ok 13 FIFO state 3: expected set; got set
15 ok 14 FIFO state 4: expected clear; got clear
16 ok 15 FIFO state 5: expected set; got set
17 ok 16 FIFO state 6: expected set; got set
18 ok 17 FIFO state 6a: expected set; got set
19 ok 18 FIFO state 6b: expected clear; got clear
[all …]
/src/tools/regression/poll/4/
H A Dpipeselect.out10 not ok 9 FIFO state 0: expected clear; got set
11 ok 10 FIFO state 1: expected clear; got clear
12 ok 11 FIFO state 2: expected set; got set
13 ok 12 FIFO state 2a: expected clear; got clear
14 ok 13 FIFO state 3: expected set; got set
15 ok 14 FIFO state 4: expected clear; got clear
16 ok 15 FIFO state 5: expected set; got set
17 ok 16 FIFO state 6: expected set; got set
18 ok 17 FIFO state 6a: expected set; got set
19 not ok 18 FIFO state 6b: expected clear; got set
[all …]
H A Dpipepoll.out10 not ok 9 FIFO state 0: expected 0; got POLLIN
11 ok 10 FIFO state 1: expected 0; got 0
12 ok 11 FIFO state 2: expected POLLIN; got POLLIN
13 ok 12 FIFO state 2a: expected 0; got 0
14 not ok 13 FIFO state 3: expected POLLHUP; got POLLIN
15 ok 14 FIFO state 4: expected 0; got 0
16 ok 15 FIFO state 5: expected POLLIN; got POLLIN
17 not ok 16 FIFO state 6: expected POLLIN | POLLHUP; got POLLIN
18 not ok 17 FIFO state 6a: expected POLLHUP; got POLLIN
19 not ok 18 FIFO state 6b: expected 0; got POLLIN
[all …]
/src/contrib/netbsd-tests/lib/libc/c063/
H A Dt_mkfifoat.c46 #define FIFO "dir/openat" macro
63 ATF_REQUIRE(access(FIFO, F_OK) == 0); in ATF_TC_BODY()
78 ATF_REQUIRE(mkfifoat(AT_FDCWD, FIFO, mode) != -1); in ATF_TC_BODY()
79 ATF_REQUIRE(access(FIFO, F_OK) == 0); in ATF_TC_BODY()
106 ATF_REQUIRE((fd = open(FIFO, O_CREAT|O_RDWR, 0644)) != -1); in ATF_TC_BODY()
108 ATF_REQUIRE(mkfifoat(-1, FIFO, mode) == -1); in ATF_TC_BODY()
/src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dcirrus,clps711x-intc.txt24 12: UTXINT1 UART1 transmit FIFO half empty
25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
30 18: SS2TX SSI2 transmit FIFO less than half empty
31 28: UTXINT2 UART2 transmit FIFO half empty
32 29: URXINT2 UART2 receive FIFO half full
/src/sys/contrib/device-tree/Bindings/serial/
H A Dmvebu-uart.txt7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
8 FIFO), called also UART1.
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
11 accesses to the FIFO), called also UART2.
/src/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpc5121-psc.txt8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
19 PSC FIFO Controller and b is a field that represents an
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
/src/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt85 Ethernet FIFO ECC
93 NAND FIFO ECC
101 DMA FIFO ECC
109 USB FIFO ECC
117 QSPI FIFO ECC
125 SDMMC FIFO ECC
268 Ethernet FIFO ECC
275 NAND FIFO ECC
282 DMA FIFO ECC
289 USB FIFO ECC
[all …]
/src/sys/dev/aic7xxx/
H A Daic79xx.seq167 * Since this status did not consume a FIFO, we have to
169 * to this transaction. There are two states that a FIFO still
172 * 1) Configured and draining to the host, with a FIFO handler.
175 * Case 1 can be detected by noticing a non-zero FIFO active
177 * the FIFO to complete the SCB.
180 * pointers for this same context in the other FIFO. So, if
306 * The FIFO use count field is shared with the
581 * Allocate a FIFO for a non-packetized transaction.
583 * can allocate a FIFO for a non-packetized transaction.
587 * Do whatever work is required to free a FIFO.
[all …]
H A Daic79xx.reg392 * Data FIFO Control
427 * Data FIFO Status
575 * Data FIFO Threshold
1081 * Data FIFO 0 PCI Status
1098 * Data FIFO 1 PCI Status
1601 * Data FIFO Status
2255 * Good Status FIFO
2265 * Data FIFO SCSI Transfer Control
2356 * Data FIFO Status
2366 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
[all …]
/src/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dath79-ddr-controller.txt4 to flush the FIFO between various devices and the DDR. This is mainly used
5 by the IRQ controller to flush the FIFO before running the interrupt handler
/src/sys/contrib/device-tree/Bindings/dma/
H A Datmel-dma.txt31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
/src/sys/contrib/device-tree/Bindings/c6x/
H A Demifa.txt22 of the oldest command in the command FIFO. Setting this field to 255
23 disables this feature, thereby allowing old commands to stay in the FIFO
/src/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-geni-qcom.txt4 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
H A Dcadence-quadspi.txt15 - cdns,fifo-depth : Size of the data FIFO in words.
16 - cdns,fifo-width : Bus width of the data FIFO in bytes.
/src/sys/contrib/device-tree/Bindings/display/tilcdc/
H A Dpanel.txt10 - fdd: FIFO DMA Request Delay
14 - fifo-th: DMA FIFO threshold
/src/sys/contrib/device-tree/Bindings/mtd/
H A Dcadence-quadspi.txt14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
/src/sys/contrib/device-tree/Bindings/security/tpm/
H A Dgoogle,cr50.txt5 SPI using the FIFO protocol described in the PTP Spec, section 6.

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