| /src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 404 unsigned ExtendOp = TargetOpcode::G_ANYEXT; in lowerReturn() local
406 ExtendOp = TargetOpcode::G_SEXT; in lowerReturn()
408 ExtendOp = TargetOpcode::G_ZEXT; in lowerReturn()
423 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
444 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 330 unsigned ExtendOp = TargetOpcode::G_ANYEXT; in lowerReturnVal() local
333 ExtendOp = TargetOpcode::G_SEXT; in lowerReturnVal()
336 ExtendOp = TargetOpcode::G_ZEXT; in lowerReturnVal()
340 extOpcodeToISDExtOpcode(ExtendOp)); in lowerReturnVal()
344 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
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| H A D | AMDGPURegisterBankInfo.cpp | 2515 unsigned ExtendOp = getExtendOp(MI.getOpcode()); in applyMappingImpl() local
2517 = unpackV2S16ToS32(B, MI.getOperand(1).getReg(), ExtendOp); in applyMappingImpl()
2519 = unpackV2S16ToS32(B, MI.getOperand(2).getReg(), ExtendOp); in applyMappingImpl()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 560 unsigned ExtendOp = TargetOpcode::G_ANYEXT) { in buildCopyToRegs() argument
569 B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg}); in buildCopyToRegs()
631 UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0); in buildCopyToRegs()
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| /src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 2117 unsigned ExtendOp = in EmitCmp() local
2119 Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0); in EmitCmp()
2120 Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1); in EmitCmp()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 884 unsigned ExtendOp = in LegalizeLoadOps() local
886 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); in LegalizeLoadOps()
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| H A D | TargetLowering.cpp | 9672 unsigned ExtendOp = ISD::getExtForLoadExtType(false, ExtType); in scalarizeVectorLoad() local
9673 Scalar = DAG.getNode(ExtendOp, SL, DstEltVT, Scalar); in scalarizeVectorLoad()
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| /src/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 1270 template <typename ExtendOp> struct ExtendOpTraits {
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22729 unsigned ExtendOp = in EmitCmp() local
22736 ExtendOp = ISD::SIGN_EXTEND; in EmitCmp()
22739 ExtendOp = ISD::SIGN_EXTEND; in EmitCmp()
22744 Op0 = DAG.getNode(ExtendOp, dl, CmpVT, Op0); in EmitCmp()
22745 Op1 = DAG.getNode(ExtendOp, dl, CmpVT, Op1); in EmitCmp()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15213 unsigned ExtendOp = in getVectorBitwiseReduce() local
15216 ExtendOp, DL, VecVT.changeVectorElementType(ExtendedVT), Vec); in getVectorBitwiseReduce()
|