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Searched refs:ElemsPerVReg (Results 1 – 1 of 1) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4075 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerBUILD_VECTOR() local
4077 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerBUILD_VECTOR()
4088 for (unsigned i = 0; i < VT.getVectorNumElements(); i += ElemsPerVReg) { in lowerBUILD_VECTOR()
4089 auto OneVRegOfOps = ArrayRef(BuildVectorOps).slice(i, ElemsPerVReg); in lowerBUILD_VECTOR()
4093 unsigned InsertIdx = (i / ElemsPerVReg) * NumOpElts; in lowerBUILD_VECTOR()
5020 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerShuffleViaVRegSplitting() local
5021 unsigned VRegsPerSrc = NumElts / ElemsPerVReg; in lowerShuffleViaVRegSplitting()
5030 int DstVecIdx = DstIdx / ElemsPerVReg; in lowerShuffleViaVRegSplitting()
5031 int DstSubIdx = DstIdx % ElemsPerVReg; in lowerShuffleViaVRegSplitting()
5035 int SrcVecIdx = SrcIdx / ElemsPerVReg; in lowerShuffleViaVRegSplitting()
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