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Searched refs:DestSub0 (Results 1 – 3 of 3) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7803 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
7804 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
7813 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp()
7817 .addReg(DestSub0) in splitScalar64BitUnaryOp()
7843 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulU64() local
7908 BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) in splitScalarSMulU64()
7923 .addReg(DestSub0) in splitScalarSMulU64()
7952 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulPseudo() local
7987 BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) in splitScalarSMulPseudo()
7992 .addReg(DestSub0) in splitScalarSMulPseudo()
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H A DSILoadStoreOptimizer.cpp1959 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local
1962 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1983 .addReg(DestSub0) in computeBase()
H A DSIISelLowering.cpp5010 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
5025 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter()
5032 .addReg(DestSub0) in EmitInstrWithCustomInserter()
5066 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
5095 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter()
5111 .addReg(DestSub0) in EmitInstrWithCustomInserter()