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Searched refs:Commutable (Results 1 – 20 of 20) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoM.td28 def MUL : ALU_rr<0b0000001, 0b000, "mul", Commutable=1>,
30 def MULH : ALU_rr<0b0000001, 0b001, "mulh", Commutable=1>,
34 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
50 def MULW : ALUW_rr<0b0000001, 0b000, "mulw", Commutable=1>,
H A DRISCVInstrInfoZfa.td85 def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, Commutable=1>;
86 def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, Commutable=1>;
106 def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, Commutable=1>;
107 def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, Commutable=1>;
147 def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, Commutable=1>;
148 def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, Commutable=1>;
H A DRISCVInstrInfoF.td191 DAGOperand rty, bit Commutable>
194 let isCommutable = Commutable;
197 ExtInfo Ext, bit Commutable = 0> {
199 def Ext.Suffix : FPALU_rr<funct7, funct3, opcodestr, Ext.PrimaryTy, Commutable>;
205 bit Commutable>
209 let isCommutable = Commutable;
212 ExtInfo Ext, bit Commutable = 0> {
214 def Ext.Suffix : FPALU_rr_frm<funct7, opcodestr, Ext.PrimaryTy, Commutable>;
270 DAGOperand rty, bit Commutable = 0>
273 let isCommutable = Commutable;
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H A DRISCVInstrInfoVPseudos.td2098 bit Commutable = 0> {
2099 let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
2117 bit Commutable = 0> {
2118 let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
2140 bit Commutable = 0> {
2141 let VLMul = MInfo.value, isCommutable = Commutable in {
2199 multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0, bit Commutable = 0> {
2200 …fm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew, Commutable=Commutable>;
2203 multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = "", bit Commutable = 0> {
2205 Commutable=Commutable>;
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H A DRISCVInstrInfoZb.td384 def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", Commutable=1>,
389 def CLMUL : ALU_rr<0b0000101, 0b001, "clmul", Commutable=1>,
391 def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", Commutable=1>,
396 def MIN : ALU_rr<0b0000101, 0b100, "min", Commutable=1>,
398 def MINU : ALU_rr<0b0000101, 0b101, "minu", Commutable=1>,
400 def MAX : ALU_rr<0b0000101, 0b110, "max", Commutable=1>,
402 def MAXU : ALU_rr<0b0000101, 0b111, "maxu", Commutable=1>,
H A DRISCVInstrInfoD.td91 defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", Ext, Commutable=1>;
95 defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", Ext, Commutable=1>;
112 defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", Ext, Commutable=1>;
113 defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", Ext, Commutable=1>;
125 defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", Ext, Commutable=1>;
H A DRISCVInstrInfoZfh.td96 defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", Ext, Commutable=1>;
100 defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", Ext, Commutable=1>;
117 defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", Ext, Commutable=1>;
118 defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", Ext, Commutable=1>;
162 defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", Ext, Commutable=1>;
H A DRISCVInstrInfo.td560 bit Commutable = 0>
563 let isCommutable = Commutable;
588 bit Commutable = 0>
591 let isCommutable = Commutable;
668 def ADD : ALU_rr<0b0000000, 0b000, "add", Commutable=1>,
680 def XOR : ALU_rr<0b0000000, 0b100, "xor", Commutable=1>,
686 def OR : ALU_rr<0b0000000, 0b110, "or", Commutable=1>,
688 def AND : ALU_rr<0b0000000, 0b111, "and", Commutable=1>,
766 def ADDW : ALUW_rr<0b0000000, 0b000, "addw", Commutable=1>,
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1021 template <typename LHS_t, typename RHS_t, bool Commutable = false>
1033 (Commutable && L.match(I->getOperand(1)) && in match()
1069 bool Commutable = false>
1082 (Commutable && L.match(I->getOperand(1)) && in match()
1242 unsigned WrapFlags = 0, bool Commutable = false>
1261 (Commutable && L.match(Op->getOperand(1)) && in match()
1344 template <typename LHS_t, typename RHS_t, bool Commutable = false>
1346 : public BinaryOp_match<LHS_t, RHS_t, 0, Commutable> {
1350 : BinaryOp_match<LHS_t, RHS_t, 0, Commutable>(LHS, RHS), Opcode(Opcode) {} in SpecificBinaryOp_match()
1353 return BinaryOp_match<LHS_t, RHS_t, 0, Commutable>::match(Opcode, V); in match()
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/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h174 Commutable, enumerator
481 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); } in isCommutable()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h391 bool Commutable = false>
404 (Commutable && (R.match(MRI, TmpMI->getOperand(1).getReg()) &&
413 template <typename LHS_P, typename RHS_P, bool Commutable = false>
429 (Commutable && (R.match(MRI, TmpMI->getOperand(1).getReg()) &&
642 bool Commutable = false>
665 if (Commutable && L.match(MRI, RHS) && R.match(MRI, LHS) &&
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Instr3DNow.td29 X86FoldableSchedWrite sched, bit Commutable = 0> {
31 let isCommutable = Commutable, mayLoad=0 in
H A DX86InstrMMX.td35 X86FoldableSchedWrite sched, bit Commutable = 0,
42 let isCommutable = Commutable;
91 bit Commutable = 0> {
92 let isCommutable = Commutable in
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2635 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2642 let isCommutable = Commutable;
2648 SDNode OpNode, bit Commutable>
2655 let isCommutable = Commutable;
2686 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2693 let isCommutable = Commutable;
2697 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2704 let isCommutable = Commutable;
2737 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2744 let isCommutable = Commutable;
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H A DARMInstrThumb2.td729 SDPatternOperator opnode, bit Commutable = 0,
747 let isCommutable = Commutable;
798 SDPatternOperator opnode, bit Commutable = 0> :
799 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
872 bit Commutable = 0> {
886 let isCommutable = Commutable;
922 bit Commutable = 0> {
1000 let isCommutable = Commutable;
1026 bit Commutable = 0, bit PostISelHook = 0> {
1043 let isCommutable = Commutable;
H A DARMInstrInfo.td1552 SDPatternOperator opnode, bit Commutable = 0> {
1577 let isCommutable = Commutable;
1698 bit Commutable = 0> {
1708 let isCommutable = Commutable;
1758 SDPatternOperator opnode, bit Commutable = 0,
1780 let isCommutable = Commutable;
1889 bit Commutable = 0> {
1914 let isCommutable = Commutable;
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSDPatternMatch.h451 template <typename T0_P, typename T1_P, typename T2_P, bool Commutable = false,
470 (Commutable && Op0.match(Ctx, N->getOperand(EO.FirstIndex + 1)) &&
494 template <typename LHS_P, typename RHS_P, bool Commutable = false,
511 (Commutable && LHS.match(Ctx, N->getOperand(EO.FirstIndex + 1)) &&
H A DMachineInstr.h1189 return hasProperty(MCID::Commutable, Type);
/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td157 string opasm, bit Commutable> {
163 { let isCommutable = Commutable; }
255 multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm, bit Commutable = 0> :
256 ArcBinaryInst<0b00100, mincode, opasm, Commutable>;
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td538 bit Commutable = 0> : R_YXZ<0x31, sop, pcode, (outs GPR:$rz),
540 let isCommutable = Commutable;