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Searched refs:CTS (Results 1 – 25 of 88) sorted by relevance

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/src/crypto/openssl/test/recipes/30-test_evp_data/
H A Devpciph_aes_cts.txt46 Cipher = AES-128-CBC-CTS
54 Cipher = AES-128-CBC-CTS
63 Cipher = AES-128-CBC-CTS
72 Cipher = AES-128-CBC-CTS
80 Cipher = AES-128-CBC-CTS
92 Cipher = AES-128-CBC-CTS
100 Cipher = AES-128-CBC-CTS
108 Cipher = AES-128-CBC-CTS
116 Cipher = AES-192-CBC-CTS
124 Cipher = AES-192-CBC-CTS
[all …]
H A Devpciph_camellia_cts.txt9 Title = Camellia CTS tests from RFC6803
37 Cipher = CAMELLIA-128-CBC-CTS
48 Cipher = CAMELLIA-128-CBC-CTS
59 Cipher = CAMELLIA-128-CBC-CTS
70 Cipher = CAMELLIA-128-CBC-CTS
81 Cipher = CAMELLIA-128-CBC-CTS
92 Cipher = CAMELLIA-256-CBC-CTS
103 Cipher = CAMELLIA-256-CBC-CTS
114 Cipher = CAMELLIA-256-CBC-CTS
125 Cipher = CAMELLIA-256-CBC-CTS
[all …]
/src/crypto/openssl/doc/man7/
H A DEVP_CIPHER-CAMELLIA.pod19 =item "CAMELLIA-128-CBC-CTS", "CAMELLIA-192-CBC-CTS" and "CAMELLIA-256-CBC-CTS"
H A DEVP_CIPHER-AES.pod20 =item "AES-128-CBC-CTS", "AES-192-CBC-CTS" and "AES-256-CBC-CTS"
77 stealing (CTS) is used to fill the block.
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-phygate-tauri-l-rs232-rts-cts.dtso6 * Tauri-L RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso5 * GW73xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso5 * GW72xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dts5 * GW73xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dts5 * GW72xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mp-dhcom-drc02.dts184 * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs
185 * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
197 * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
H A Dimx8mq-hummingboard-pulse.dts166 * reconfigured to enable RTS/CTS on UART3
209 * Header. To use RTS/CTS on UART3 comment them out
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYAsmPrinter.cpp136 CSKYTargetStreamer &CTS = in emitEndOfAsmFile() local
140 CTS.finishAttributeSection(); in emitEndOfAsmFile()
249 CSKYTargetStreamer &CTS = in emitAttributes() local
260 CTS.emitTargetAttributes(STI); in emitAttributes()
/src/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp153c-lxa-fairytux2-gen1.dts94 * On Gen 1 FairyTux 2 only RTS can be used and not CTS as well,
95 * Because pins PD11 (CTS) and PI11 (USER_BTN1) share the same
H A Dste-dbx5x0-pinctrl.dtsi17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
75 pins = "GPIO6_AF6"; /* CTS */
86 pins = "GPIO6_AF6"; /* CTS */
/src/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-mxs-auart.txt22 - uart-has-rtscts : Indicate the UART has RTS and CTS lines
25 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
H A Dmicrochip,pic32-uart.txt14 - cts-gpios: CTS pin for UART
H A Dcirrus,clps711x-uart.txt11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
H A Dcdns,uart.txt16 - cts-override : Override the CTS modem status signal. This signal will
/src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ull-dhcom-drc02.dts23 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
24 * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
H A Dimx6ul-ccimx6ulsbcpro.dts62 /* CAN2 is multiplexed with UART2 RTS/CTS */
200 /* UART2 RTS/CTS muxed with CAN2 */
208 /* UART3 RTS/CTS muxed with CAN 1 */
/src/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-netcom-plus-2xx.dts25 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
38 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
/src/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a64-sopine-baseboard.dts189 /* On Wifi/BT connector, with RTS/CTS */
211 /* On Euler connector, RTS/CTS optional */
H A Dsun50i-a64-orangepi-win.dts382 /* On Pi-2 connector, RTS/CTS optional */
389 /* On Pi-2 connector, RTS/CTS optional */
396 /* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
/src/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dserial.txt14 CTS, RTS, DCD, DSR, DTR, and RI.
/src/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a08g045s33-smarc-pmod1-type-3a.dtso36 <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS# */

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