Searched refs:CPM (Results 1 – 13 of 13) sorted by relevance
1 PPC4xx Clock Power Management (CPM) node9 - er-offset : All 4xx SoCs with a CPM controller have10 one of two different order for the CPM11 registers. Some have the CPM registers18 in CPM will be set to turn off unused22 in CPM will be set to turn off unused23 devices. This is usually just CPM[CPU].26 in CPM will be set on standby and30 in CPM will be set on suspend (mem) and
7 * Root CPM node22 * Properties common to multiple CPM/QE devices25 to specify the device on which a CPM command operates.38 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.47 CPM-side offsets with pointer subtraction. It is recommended that
5 in with the CPM binding later in this document.17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
24 QE and two options for CPM.
18 CPM UART driver, the port-number is required for the QE UART driver.
3 The I2C controller is expressed as a bus under the CPM node.
65 /* CON15,16 - CPM lane 4 */245 /* CPM Lane 5 - U29 */
145 * SPI on CPM and NAND have common pins on this board. We can
476 * this controller is only usable on the CPM
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
764 * Since our pcie doesn't support ClockPM(CPM), we want766 * de-assert it along and make ClockPM(CPM) work.
105 else if (auto *CPM = dyn_cast<CheckComplexPatMatcher>(N)) in MatcherTableEmitter() local106 ++ComplexPatternUsage[&CPM->getPattern()]; in MatcherTableEmitter()
9481 @Article{Wagner:1973:CPM,