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Searched refs:CLK (Results 1 – 25 of 55) sorted by relevance

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/src/sys/dev/kbd/
H A Dkbdtables.h103 /*3a*/{{ CLK, CLK, CLK, CLK, CLK, CLK, CLK, CLK, }, 0xFF,0x00 },
/src/sys/contrib/device-tree/src/arm/st/
H A Dste-dbx5x0-pinctrl.dtsi267 pins = "GPIO23_AA4"; /* CLK */
300 pins = "GPIO23_AA4"; /* CLK */
315 pins = "GPIO23_AA4"; /* CLK */
341 pins = "GPIO23_AA4"; /* CLK */
355 pins = "GPIO208_AH16"; /* CLK */
375 pins = "GPIO208_AH16"; /* CLK */
396 pins = "GPIO208_AH16"; /* CLK */
412 pins = "GPIO208_AH16"; /* CLK */
435 pins = "GPIO128_A5"; /* CLK */
464 pins = "GPIO128_A5"; /* CLK */
[all …]
H A Dstm32f7-pinctrl.dtsi241 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
254 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
272 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
283 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
296 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
314 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
H A Dste-href-family-pinctrl.dtsi29 "GPIO217_AH12"; /* CLK */
49 pins = "GPIO217_AH12"; /* CLK */
66 pins = "GPIO217_AH12"; /* CLK */
/src/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap5-dss.txt77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
99 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,omap4-dss.txt96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
118 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,dra7-dss.txt73 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,omap3-dss.txt86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/src/sys/contrib/device-tree/Bindings/media/
H A Drenesas,drif.txt8 | |-----SCK------->|CLK |
16 CLK & SYNC. Each internal channel has its own dedicated resources like
21 The internal channels sharing the CLK & SYNC are tied together by their
91 | |-----SCK------->|CLK |
139 | |-----SCK------->|CLK |
/src/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8992-pins.dtsi33 /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */
34 /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */
H A Dsm8750.dtsi2880 /* MISO, MOSI, CLK */
2895 /* MISO, MOSI, CLK */
2910 /* MISO, MOSI, CLK */
2925 /* MISO, MOSI, CLK */
2940 /* MISO, MOSI, CLK */
2955 /* MISO, MOSI, CLK */
2970 /* MISO, MOSI, CLK */
2985 /* MISO, MOSI, CLK */
3000 /* MISO, MOSI, CLK */
3015 /* MISO, MOSI, CLK */
[all …]
H A Dsar2130p.dtsi2615 /* MISO, MOSI, CLK */
2630 /* MISO, MOSI, CLK */
2645 /* MISO, MOSI, CLK */
2667 /* MISO, MOSI, CLK */
2689 /* MISO, MOSI, CLK */
2704 /* MISO, MOSI, CLK */
2719 /* MISO, MOSI, CLK */
2734 /* MISO, MOSI, CLK */
2749 /* MISO, MOSI, CLK */
2764 /* MISO, MOSI, CLK */
[all …]
/src/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl-s905x-khadas-vim.dts189 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
198 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
201 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
H A Dmeson-gxbb-nanopi-k2.dts266 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
285 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
288 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
/src/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a07g043u11-smarc-du-adv7513.dtso59 pinmux = <RZG2L_PORT_PINMUX(11, 3, 6)>; /* CLK */
H A Dr8a779g3-sparrow-hawk.dts133 /* Page 26 / PCIe.0/1 CLK */
280 line-name = "PCIe-CLK-nOE-M2";
288 line-name = "PCIe-CLK-nOE-USB";
415 /* Page 26 / PCIe.0/1 CLK */
/src/sys/contrib/device-tree/Bindings/hwmon/
H A Dg762.txt8 on CLK pin of the chip.
/src/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-h2-plus-bananapi-m2-zero.dts234 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
241 "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
H A Dsun7i-a20-bananapi.dts256 "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3",
273 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
H A Dsun6i-a31s-sinovoip-bpi-m2.dts281 "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK",
302 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx95-phycore-fpsc.dtsi564 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e /* CLK */
578 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e /* CLK */
591 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe /* CLK */
/src/sys/contrib/device-tree/Bindings/gpio/
H A Dsgpio-aspeed.txt27 - bus-frequency : SGPM CLK frequency
/src/sys/sys/
H A Dkbio.h149 #define CLK 0x04 /* caps lock key */ macro
/src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7622-rfb1.dts277 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
421 * DAT2, DAT3, CMD, CLK for SD respectively.
H A Dmt7622-bananapi-bpi-r64.dts338 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
487 * DAT2, DAT3, CMD, CLK for SD respectively.

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