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Searched refs:BW (Results 1 – 25 of 62) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp161 unsigned BW = Ty->getPrimitiveSizeInBits(); in INITIALIZE_PASS_DEPENDENCY() local
162 if (BW != 32 && BW != 64) in INITIALIZE_PASS_DEPENDENCY()
174 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL); in INITIALIZE_PASS_DEPENDENCY()
185 uint32_t U = BW - std::max(SL, SR); in INITIALIZE_PASS_DEPENDENCY()
200 APInt C = APInt::getHighBitsSet(BW, BW-U); in INITIALIZE_PASS_DEPENDENCY()
212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
300 while (I*BW < Ws) { in evaluate()
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
H A DHexagonConstPropagation.cpp1588 unsigned BW = A1.getBitWidth(); in evaluateZEXTi() local
1589 (void)BW; in evaluateZEXTi()
1590 assert(Width >= Bits && BW >= Bits); in evaluateZEXTi()
1619 unsigned BW = A1.getBitWidth(); in evaluateSEXTi() local
1620 assert(Width >= Bits && BW >= Bits); in evaluateSEXTi()
1629 if (BW <= 64 && Bits != 0) { in evaluateSEXTi()
1654 if (Bits < BW) in evaluateSEXTi()
1684 unsigned BW = A1.getBitWidth(); in evaluateCLBi() local
1692 Result = APInt(BW, static_cast<uint64_t>(Count), false); in evaluateCLBi()
1719 unsigned BW = A1.getBitWidth(); in evaluateCTBi() local
[all …]
H A DBitTracker.cpp350 uint16_t BW = getRegBitWidth(RR); in getCell() local
355 return RegisterCell::self(0, BW); in getCell()
362 return RegisterCell::self(0, BW); in getCell()
372 return RegisterCell::top(BW); in getCell()
424 uint16_t BW = A.getBitWidth(); in eIMM() local
425 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); in eIMM()
426 RegisterCell Res(BW); in eIMM()
427 for (uint16_t i = 0; i < BW; ++i) in eIMM()
H A DHexagonExpandCondsets.cpp238 bool isIntReg(RegisterRef RR, unsigned &BW);
1118 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() argument
1123 BW = 32; in isIntReg()
1127 BW = (RR.Sub != 0) ? 32 : 64; in isIntReg()
H A DHexagonBitSimplify.cpp1363 unsigned BN, BW; in processBlock() local
1364 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in processBlock()
1368 if (!usedBitsEqual(RD, RS) && !HBS::isEqual(DC, 0, SC, BN, BW)) in processBlock()
2183 unsigned BN, BW; in genExtractLow() local
2184 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in genExtractLow()
2186 if (BW < W || !HBS::isEqual(RC, 0, SC, BN, W)) in genExtractLow()
H A DHexagonPatternsHVX.td674 // Do it as (Vu << Vs) | (Vv >> (BW-Vs)).
675 // For Vs == 0 becomes Vu | (Vv >> -BW), since the shift amount is
676 // sign-extended. Then this becomes Vu | (Vv << BW) == Vu.
715 // Do it as (Vu >> -(BW-Vs)) | (Vv >> Vs).
716 // For Vs == 0 becomes (Vu << BW) | Vs == 0 | Vv
/src/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp445 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in generateCondForPow() local
447 if (BW == 8) in generateCondForPow()
449 else if (BW == 16) in generateCondForPow()
451 else if (BW == 32) in generateCondForPow()
/src/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DValueLattice.h284 ConstantRange asConstantRange(unsigned BW, bool UndefAllowed = false) const {
290 return ConstantRange::getEmpty(BW);
291 return ConstantRange::getFull(BW);
/src/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp842 unsigned BW = DL.getIndexTypeSizeInBits(PtrOp->getType()); in getStrideAndModOffsetOfGEP() local
844 APInt ModOffset(BW, 0); in getStrideAndModOffsetOfGEP()
849 if (!GEP->collectOffset(DL, BW, VarOffsets, ModOffset)) in getStrideAndModOffsetOfGEP()
869 return {APInt(BW, 1), APInt(BW, 0)}; in getStrideAndModOffsetOfGEP()
901 unsigned BW = DL.getIndexTypeSizeInBits(PtrOp->getType()); in foldPatternedLoads() local
909 ConstOffset = APInt(BW, 0); in foldPatternedLoads()
910 Stride = APInt(BW, LA.value()); in foldPatternedLoads()
/src/contrib/llvm-project/llvm/lib/IR/
H A DConstantRange.cpp798 auto BW = getBitWidth(); in castOp() local
799 APInt Min = APInt::getMinValue(BW); in castOp()
800 APInt Max = APInt::getMaxValue(BW); in castOp()
801 if (ResultBitWidth > BW) { in castOp()
809 auto BW = getBitWidth(); in castOp() local
810 APInt SMin = APInt::getSignedMinValue(BW); in castOp()
811 APInt SMax = APInt::getSignedMaxValue(BW); in castOp()
812 if (ResultBitWidth > BW) { in castOp()
1574 unsigned BW = getBitWidth(); in shl() local
1575 if (RHS->uge(BW)) in shl()
[all …]
/src/contrib/llvm-project/llvm/include/llvm/ADT/
H A DBitVector.h809 BitWord BW = Bits[i]; in applyMask() local
814 if (AddBits) BW |= BitWord(M) << b; in applyMask()
815 else BW &= ~(BitWord(M) << b); in applyMask()
817 Bits[i] = BW; in applyMask()
/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp452 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConstVector() local
453 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW, in getOrCreateConstVector()
471 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConstVector() local
472 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW, in getOrCreateConstVector()
486 unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy); in getOrCreateConstIntArray() local
498 return getOrCreateCompositeOrNull(CI, I, SpvType, TII, UniqueKey, BW, in getOrCreateConstIntArray()
550 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConsIntVector() local
552 ConstVec, BW, in getOrCreateConsIntVector()
/src/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp173 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
174 auto Input = ConstantRange::getFull(BW); in walkBackwards()
H A DConstantHoisting.cpp543 unsigned BW = V1.getBitWidth() > V2.getBitWidth() ? in calculateOffsetDiff() local
552 return APInt(BW, Diff, true); in calculateOffsetDiff()
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1210 unsigned BW = VT.getScalarSizeInBits(); in ExpandSEXTINREG() local
1212 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); in ExpandSEXTINREG()
1611 unsigned BW = VT.getScalarSizeInBits(); in ExpandUINT_TO_FLOAT() local
1612 assert((BW == 64 || BW == 32) && in ExpandUINT_TO_FLOAT()
1615 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT); in ExpandUINT_TO_FLOAT()
1620 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF; in ExpandUINT_TO_FLOAT()
1625 DAG.getConstantFP(1ULL << (BW / 2), DL, Node->getValueType(0)); in ExpandUINT_TO_FLOAT()
/src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp269 unsigned BW = X->getType()->getScalarSizeInBits(); in visitImpl() local
270 Constant *BWMinusOne = ConstantInt::get(X->getType(), BW - 1); in visitImpl()
/src/contrib/llvm-project/clang/include/clang/AST/
H A DDeclObjC.h1961 TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, in ObjCIvarDecl() argument
1963 : FieldDecl(ObjCIvar, DC, StartLoc, IdLoc, Id, T, TInfo, BW, in ObjCIvarDecl()
1972 Expr *BW = nullptr, bool synthesized = false);
2031 QualType T, Expr *BW) in ObjCAtDefsFieldDecl() argument
2034 BW, /*Mutable=*/false, /*HasInit=*/ICIS_NoInit) {} in ObjCAtDefsFieldDecl()
2042 QualType T, Expr *BW);
/src/contrib/llvm-project/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp1296 unsigned BW = OffsetRange.getBitWidth(); in aliasGEP() local
1298 ConstantRange(APInt(BW, 0), APInt(BW, V1Size.getValue()))); in aliasGEP()
1300 ConstantRange(APInt(BW, 0), APInt(BW, V2Size.getValue())); in aliasGEP()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td444 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
447 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
451 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
452 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp404 unsigned BW = DL.getIndexTypeSizeInBits(GEP->getType()); in GEPToVectorIndex() local
406 APInt ConstOffset(BW, 0); in GEPToVectorIndex()
408 !GEP->collectOffset(DL, BW, VarOffsets, ConstOffset)) in GEPToVectorIndex()
/src/contrib/llvm-project/clang/lib/AST/
H A DDeclObjC.cpp1838 Expr *BW, bool synthesized) { in Create() argument
1865 return new (C, DC) ObjCIvarDecl(DC, StartLoc, IdLoc, Id, T, TInfo, ac, BW, in Create()
1913 IdentifierInfo *Id, QualType T, Expr *BW) { in Create() argument
1914 return new (C, DC) ObjCAtDefsFieldDecl(DC, StartLoc, IdLoc, Id, T, BW); in Create()
/src/contrib/libdivsufsort/include/
H A Ddivsufsort.h.cmake115 * Inverse BW-transforms a given BWTed string.
/src/sys/dev/ena/
H A Dena_sysctl.c105 bw_in_allowance_exceeded, Inbound BW allowance exceeded),
107 bw_out_allowance_exceeded, Outbound BW allowance exceeded),

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