| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SLSHardening.cpp | 180 case AArch64::BLR: in getThunkKind()
422 MachineInstr &BLR = *MBBI; in convertBLRToBL() local
423 assert(isBLR(BLR)); in convertBLRToBL()
424 const ThunkKind &Kind = *getThunkKind(BLR.getOpcode()); in convertBLRToBL()
427 assert(BLR.getNumExplicitOperands() == NumRegOperands && in convertBLRToBL()
429 Register Xn = BLR.getOperand(0).getReg(); in convertBLRToBL()
431 Kind.HasXmOperand ? BLR.getOperand(1).getReg() : AArch64::NoRegister; in convertBLRToBL()
433 DebugLoc DL = BLR.getDebugLoc(); in convertBLRToBL()
477 BL->copyImplicitOps(MF, BLR); in convertBLRToBL()
478 MF.moveCallSiteInfo(&BLR, BL); in convertBLRToBL()
[all …]
|
| H A D | AArch64SchedPredExynos.td | 27 // Identify BLR specifying the LR register as the indirect target register.
29 CheckAll<[CheckOpcode<[BLR]>,
|
| H A D | AArch64SchedThunderX.td | 258 def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>;
|
| H A D | AArch64AsmPrinter.cpp | 1614 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); in LowerPATCHPOINT()
1650 CallOpcode = AArch64::BLR; in LowerSTATEPOINT()
2622 Blr.setOpcode(AArch64::BLR); in emitInstruction()
|
| H A D | AArch64SchedTSV110.td | 345 def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BLR)>;
|
| H A D | AArch64SchedExynosM3.td | 496 def : InstRW<[M3WriteBX], (instrs BLR)>;
|
| H A D | AArch64Features.td | 878 "Harden against straight line speculation across BLR instructions">;
|
| H A D | AArch64SchedA57.td | 141 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
|
| H A D | AArch64SchedAmpere1B.td | 651 def : InstRW<[Ampere1BWrite_1cyc_2A], (instrs BLR)>;
|
| H A D | AArch64SchedAmpere1.td | 695 def : InstRW<[Ampere1Write_1cyc_2A], (instrs BLR)>;
|
| H A D | AArch64ExpandPseudoInsts.cpp | 828 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR; in createCall()
|
| H A D | AArch64SchedNeoverseN1.td | 285 def : InstRW<[N1Write_1c_1B_1I], (instrs BL, BLR)>;
|
| H A D | AArch64SchedExynosM4.td | 592 def : InstRW<[M4WriteBX], (instrs BLR)>;
|
| H A D | AArch64SchedExynosM5.td | 627 def : InstRW<[M5WriteBX], (instrs BLR)>;
|
| H A D | AArch64InstrInfo.cpp | 8517 ((LastInstrOpcode == AArch64::BLR || in getOutliningCandidateInfo()
8969 if (MI.getOpcode() == AArch64::BLR || in getOutliningTypeImpl()
9071 assert(Call->getOpcode() == AArch64::BLR || in buildOutlinedFrame()
9535 return AArch64::BLR; in getBLRCallOpcode()
|
| H A D | AArch64SchedOryon.td | 725 def : InstRW<[ORYONWrite_1Cyc_I0], (instrs BR, BLR)>;
|
| H A D | AArch64SchedFalkorDetails.td | 1077 def : InstRW<[FalkorWr_1Z_1XY_0cyc], (instrs BLR)>;
|
| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCEarlyReturn.cpp | 60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
|
| H A D | PPCScheduleP7.td | 123 BDZLR, BDZLR8, BDZLRL, BDZLRLm, BLR, BLR8, BLRL, BCL, BCLR, BCLRL, BCLRLn,
|
| H A D | P10InstrResources.td | 319 …OP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP…
|
| H A D | P9InstrResources.td | 1307 (instregex "BLR(8|L)?$"),
|
| H A D | PPCInstrInfo.cpp | 95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
2180 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
|
| H A D | PPCFrameLowering.cpp | 1884 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && in emitEpilogue()
|
| /src/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetInstrPredicate.td | 17 // CheckOpcode<[BLR]>,
26 // whose opcode is BLR, and whose first operand is a register different from
45 // MI->getOpcode() == AArch64::BLR &&
|
| /src/share/misc/ |
| H A D | iso3166 | 41 BY BLR 112 Belarus
|