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Searched refs:BIC (Results 1 – 25 of 34) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td367 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>;
368 def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "(BIC)S[WX]rr")>;
373 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
383 def : InstRW<[TSV110WrISReg], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]rs$")>;
388 def : InstRW<[TSV110WrISRegBr], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)S[WX]rs$")>;
578 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")…
H A DAArch64SchedCyclone.td143 // ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr
157 // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
376 // BIC,ORR V,#imm are WriteV
416 // AND,BIC,CMTST,EOR,ORN,ORR
H A DAArch64SchedExynosM5.td635 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
636 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
639 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>;
640 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>;
791 def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
H A DAArch64SchedAmpere1B.td921 (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[sx]")>;
923 (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[ri]")>;
925 (instregex "(ADD|AND|BIC|SUB)S[WX]r[sx]")>;
927 (instregex "(ADD|AND|BIC|SUB)S[WX]r[ri]")>;
H A DAArch64SchedAmpere1.td939 (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)(W|X)r[sx]")>;
941 (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)(W|X)r[ri]")>;
943 (instregex "(ADD|AND|BIC|SUB)S(W|X)r[sx]")>;
945 (instregex "(ADD|AND|BIC|SUB)S(W|X)r[ri]")>;
H A DAArch64SchedNeoverseV1.td519 "^(AND|BIC)S[WX]rr$")>;
540 def : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
543 def : InstRW<[V1Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>;
1339 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;
1343 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)S_PPzPP$")>;
1384 "^(AND|BIC|EOR|EOR(BT|TB)?|ORR)_ZP?ZZ",
1386 "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]")>;
H A DAArch64SchedA510.td436 "(ORR|BIC)v(2i32|4i16|8i8)$", "MVNIv(2i|2s|4i16)")>;
438 "(ORR|BIC)v(16i8|4i32|8i16)$", "MVNIv(4i32|4s|8i16)")>;
598 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;
863 "^(AND|BIC|EOR|EOR|ORR)_ZZZ",
864 "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]",
865 "^(AND|BIC|EOR|NOT|ORR)_ZPZZ_[BHSD]")>;
H A DAArch64SchedFalkorDetails.td660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
661 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIC|ORR)(v2i32|v4i16)$")>;
724 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
725 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>;
896 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^BIC(S)?(W|X)r(r|s)$")>;
H A DAArch64SchedExynosM3.td501 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
504 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
621 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
H A DAArch64SchedThunderX3T110.td689 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
711 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
730 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
1342 // ASIMD logical (AND, BIC, EOR)
1470 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
H A DAArch64SchedThunderX2T99.td429 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
451 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
470 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
1234 // ASIMD logical (AND, BIC, EOR)
1362 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
H A DAArch64SchedA55.td424 "(ORR|BIC)v(2i32|4i16|8i8)$", "MVNIv(2i|2s|4i16)")>;
426 "(ORR|BIC)v(16i8|4i32|8i16)$", "MVNIv(4i32|4s|8i16)")>;
H A DAArch64SchedExynosM4.td597 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
599 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
743 def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
H A DAArch64SchedA64FX.td605 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
625 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
642 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
1362 // ASIMD logical (AND, BIC, EOR)
1498 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;
H A DAArch64SchedNeoverseN2.td658 (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
661 def : InstRW<[N2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
1543 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;
1782 "^(AND|BIC|EOR|ORR)_ZZZ",
1784 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",
H A DAArch64SchedKryoDetails.td435 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
441 …(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))…
453 (instregex "(BIC|ORR)S?Wri")>;
459 (instregex "(BIC|ORR)S?Xri")>;
H A DAArch64SchedNeoverseV2.td1145 def : InstRW<[V2Write_1cyc_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
1149 def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
2052 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;
2293 "^(AND|BIC|EOR|ORR)_ZZZ",
2295 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",
H A DAArch64SchedNeoverseN1.td318 (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
321 def : InstRW<[N1Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>;
H A DAArch64ISelLowering.h140 BIC, enumerator
H A DAArch64SchedOryon.td752 "^ORR(W|X)r(i|r|x)", "^BIC(W|X)r(i|r|x)",
758 "^BIC(W|X)rs", "^EON(W|X)rs", "^ORN(W|X)rs")>;
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM85.td412 (instregex "t2(ADC|ADDS|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|"
421 (instregex "t2(ADC|ADDS|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|"
H A DARMScheduleM7.td326 (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
H A DARMScheduleSwift.td130 // AND,BIC,EOR,ORN,ORR
H A DARMScheduleA57.td170 // ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},
/src/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td547 defm BIC : Arith<0b1100, "bic", bic, 0, []>;

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