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Searched refs:AddrIndexReg (Results 1 – 19 of 19) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InsertPrefetch.cpp86 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch()
227 X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && in runOnMachineFunction()
238 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg()) in runOnMachineFunction()
H A DX86FixupLEAs.cpp459 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage()
508 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU()
556 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in optTwoAddrLEA()
661 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
696 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstructionForSlowLEA()
748 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstrForSlow3OpLEA()
H A DX86AsmPrinter.cpp377 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference()
417 PrintModifiedOperand(MI, OpNo + X86::AddrIndexReg, O, Modifier); in PrintLeaMemReference()
474 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference()
508 PrintOperand(MI, OpNo + X86::AddrIndexReg, O); in PrintIntelMemReference()
H A DX86OptimizeLEAs.cpp196 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey()
560 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
H A DX86CallFrameOptimization.cpp431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
H A DX86SpeculativeLoadHardening.cpp1334 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1405 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1805 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
H A DX86InstrInfo.h163 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
H A DX86AvoidStoreForwardingBlocks.cpp317 const MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); in isRelevantAddressingMode()
H A DX86InstrInfo.cpp479 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand()
482 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand()
931 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
932 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
951 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
952 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
3609 const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg); in getConstantFromPool()
4509 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp()
4633 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOperandsWithOffsetWidth()
4699 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg); in loadStoreTileReg()
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H A DX86LoadValueInjectionLoadHardening.cpp783 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in instrUsesRegToAccessMemory()
H A DX86ExpandPseudo.cpp658 Register Index = MI.getOperand(MemOpNo + X86::AddrIndexReg).getReg(); in expandMI()
H A DX86FastISel.cpp219 X86::AddrIndexReg); in addFullAddress()
/src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp615 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte()
1069 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1088 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1089 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix()
1135 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1136 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix()
1149 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1158 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1180 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1181 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix()
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H A DX86MCTargetDesc.cpp79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand()
666 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress()
692 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset()
H A DX86ATTInstPrinter.cpp427 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
451 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
H A DX86IntelInstPrinter.cpp385 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference()
404 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
H A DX86EncodingOptimization.cpp382 MI.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in optimizeMOV()
H A DX86BaseInfo.h31 AddrIndexReg = 2, enumerator
/src/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp3863 Inst.getOperand(4 + X86::AddrIndexReg).getReg()); in validateInstruction()
3871 Inst.getOperand(3 + X86::AddrIndexReg).getReg()); in validateInstruction()