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Searched refs:AVR (Results 1 – 25 of 53) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRELFObjectWriter.cpp81 case AVR::fixup_32: in getRelocType()
83 case AVR::fixup_7_pcrel: in getRelocType()
85 case AVR::fixup_13_pcrel: in getRelocType()
87 case AVR::fixup_16: in getRelocType()
89 case AVR::fixup_16_pm: in getRelocType()
91 case AVR::fixup_lo8_ldi: in getRelocType()
93 case AVR::fixup_hi8_ldi: in getRelocType()
95 case AVR::fixup_hh8_ldi: in getRelocType()
97 case AVR::fixup_lo8_ldi_neg: in getRelocType()
99 case AVR::fixup_hi8_ldi_neg: in getRelocType()
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H A DAVRELFStreamer.cpp17 if (Features[AVR::ELFArchAVR1]) in getEFlagsForFeatureSet()
19 else if (Features[AVR::ELFArchAVR2]) in getEFlagsForFeatureSet()
21 else if (Features[AVR::ELFArchAVR25]) in getEFlagsForFeatureSet()
23 else if (Features[AVR::ELFArchAVR3]) in getEFlagsForFeatureSet()
25 else if (Features[AVR::ELFArchAVR31]) in getEFlagsForFeatureSet()
27 else if (Features[AVR::ELFArchAVR35]) in getEFlagsForFeatureSet()
29 else if (Features[AVR::ELFArchAVR4]) in getEFlagsForFeatureSet()
31 else if (Features[AVR::ELFArchAVR5]) in getEFlagsForFeatureSet()
33 else if (Features[AVR::ELFArchAVR51]) in getEFlagsForFeatureSet()
35 else if (Features[AVR::ELFArchAVR6]) in getEFlagsForFeatureSet()
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H A DAVRAsmBackend.cpp85 AVR::fixups::adjustBranchTarget(Value); in adjustBranch()
99 AVR::fixups::adjustBranchTarget(Value); in adjustRelativeBranch()
266 case AVR::fixup_7_pcrel: in adjustFixupValue()
269 case AVR::fixup_13_pcrel: in adjustFixupValue()
272 case AVR::fixup_call: in adjustFixupValue()
275 case AVR::fixup_ldi: in adjustFixupValue()
278 case AVR::fixup_lo8_ldi: in adjustFixupValue()
281 case AVR::fixup_lo8_ldi_pm: in adjustFixupValue()
282 case AVR::fixup_lo8_ldi_gs: in adjustFixupValue()
286 case AVR::fixup_hi8_ldi: in adjustFixupValue()
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H A DAVRMCExpr.cpp148 AVR::Fixups AVRMCExpr::getFixupKind() const { in getFixupKind()
149 AVR::Fixups Kind = AVR::Fixups::LastTargetFixupKind; in getFixupKind()
153 Kind = isNegated() ? AVR::fixup_lo8_ldi_neg : AVR::fixup_lo8_ldi; in getFixupKind()
156 Kind = isNegated() ? AVR::fixup_hi8_ldi_neg : AVR::fixup_hi8_ldi; in getFixupKind()
159 Kind = isNegated() ? AVR::fixup_hh8_ldi_neg : AVR::fixup_hh8_ldi; in getFixupKind()
162 Kind = isNegated() ? AVR::fixup_ms8_ldi_neg : AVR::fixup_ms8_ldi; in getFixupKind()
166 Kind = isNegated() ? AVR::fixup_lo8_ldi_pm_neg : AVR::fixup_lo8_ldi_pm; in getFixupKind()
169 Kind = isNegated() ? AVR::fixup_hi8_ldi_pm_neg : AVR::fixup_hi8_ldi_pm; in getFixupKind()
172 Kind = isNegated() ? AVR::fixup_hh8_ldi_pm_neg : AVR::fixup_hh8_ldi_pm; in getFixupKind()
176 Kind = AVR::fixup_16_pm; in getFixupKind()
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H A DAVRInstPrinter.cpp44 case AVR::LDRdPtr: in printInst()
45 case AVR::LDRdPtrPi: in printInst()
46 case AVR::LDRdPtrPd: in printInst()
51 if (Opcode == AVR::LDRdPtrPd) in printInst()
56 if (Opcode == AVR::LDRdPtrPi) in printInst()
59 case AVR::STPtrRr: in printInst()
65 case AVR::STPtrPiRr: in printInst()
66 case AVR::STPtrPdRr: in printInst()
69 if (Opcode == AVR::STPtrPdRr) in printInst()
74 if (Opcode == AVR::STPtrPiRr) in printInst()
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H A DAVRMCCodeEmitter.cpp77 bool IsRegX = MI.getOperand(0).getReg() == AVR::R27R26 || in loadStorePostEncoder()
78 MI.getOperand(1).getReg() == AVR::R27R26; in loadStorePostEncoder()
80 bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr; in loadStorePostEncoder()
81 bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr; in loadStorePostEncoder()
91 template <AVR::Fixups Fixup>
109 AVR::fixups::adjustBranchTarget(target); in encodeRelCondBrTarget()
122 case AVR::R27R26: in encodeLDSTPtrReg()
124 case AVR::R29R28: in encodeLDSTPtrReg()
126 case AVR::R31R30: in encodeLDSTPtrReg()
151 case AVR::R31R30: in encodeMemri()
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H A DAVRMCCodeEmitter.h50 template <AVR::Fixups Fixup>
72 template <AVR::Fixups Fixup, unsigned Offset>
/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp39 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(), in AVRInstrInfo()
49 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
67 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi) in copyPhysReg()
69 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo) in copyPhysReg()
72 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo) in copyPhysReg()
74 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi) in copyPhysReg()
79 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
80 Opc = AVR::MOVRdRr; in copyPhysReg()
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H A DAVRRegisterInfo.cpp61 Reserved.set(AVR::R0); in getReservedRegs()
62 Reserved.set(AVR::R1); in getReservedRegs()
63 Reserved.set(AVR::R1R0); in getReservedRegs()
66 Reserved.set(AVR::SPL); in getReservedRegs()
67 Reserved.set(AVR::SPH); in getReservedRegs()
68 Reserved.set(AVR::SP); in getReservedRegs()
73 for (unsigned Reg = AVR::R2; Reg <= AVR::R17; Reg++) in getReservedRegs()
76 for (unsigned Reg = AVR::R3R2; Reg <= AVR::R18R17; Reg++) in getReservedRegs()
89 Reserved.set(AVR::R28); in getReservedRegs()
90 Reserved.set(AVR::R29); in getReservedRegs()
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H A DAVRFrameLowering.cpp62 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
74 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister()) in emitPrologue()
77 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
103 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) { in emitPrologue()
108 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
109 .addReg(AVR::SP) in emitPrologue()
114 MBBJ.addLiveIn(AVR::R29R28); in emitPrologue()
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H A DAVRExpandPseudoInsts.cpp222 if (Op == AVR::ANDIRdK && ImmVal == 0xff) in isLogicImmOpRedundant()
226 if (Op == AVR::ORIRdK && ImmVal == 0x0) in isLogicImmOpRedundant()
234 if (Op == AVR::ANDIRdK && ImmVal == 0x00) in isLogicRegOpUndef()
238 if (Op == AVR::ORIRdK && ImmVal == 0xff) in isLogicRegOpUndef()
289 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) { in expand()
290 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI); in expand()
294 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) { in expand()
295 return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI); in expand()
299 bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) { in expand()
300 return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI); in expand()
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H A DAVRISelLowering.cpp40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
49 setStackPointerRegisterToSaveRestore(AVR::SP); in AVRTargetLowering()
1053 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { in isLegalAddressingMode()
1084 if (AVR::isProgramMemoryAccess(LD)) { in getPreIndexedAddressParts()
1090 if (AVR::isProgramMemoryAccess(ST)) { in getPreIndexedAddressParts()
1142 if (AVR::isProgramMemoryAccess(ST)) in getPostIndexedAddressParts()
1173 if (AVR::isProgramMemoryAccess(LD)) in getPostIndexedAddressParts()
1200 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1201 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
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H A DAVRTargetObjectFile.cpp43 if (AVR::isProgramMemoryAddress(GO) && !GO->hasSection() && in SelectSectionForGlobal()
56 AVR::getAddressSpace(GO) != AVR::ProgramMemory) { in SelectSectionForGlobal()
63 switch (AVR::getAddressSpace(GO)) { in SelectSectionForGlobal()
64 case AVR::ProgramMemory: // address space 1 in SelectSectionForGlobal()
66 case AVR::ProgramMemory1: // address space 2 in SelectSectionForGlobal()
68 case AVR::ProgramMemory2: // address space 3 in SelectSectionForGlobal()
70 case AVR::ProgramMemory3: // address space 4 in SelectSectionForGlobal()
72 case AVR::ProgramMemory4: // address space 5 in SelectSectionForGlobal()
74 case AVR::ProgramMemory5: // address space 6 in SelectSectionForGlobal()
H A DAVRISelDAGToDAG.cpp165 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi; in selectIndexedLoad()
173 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi; in selectIndexedLoad()
204 Opcode = AVR::LPMRdZPi; in selectIndexedProgMemLoad()
231 RI.getRegClass(RegNode->getReg()) == &AVR::PTRDISPREGSRegClass) { in SelectInlineAsmMemoryOperand()
264 AVR::PTRDISPREGSRegClass.contains(Reg)); in SelectInlineAsmMemoryOperand()
274 if (RI.getRegClass(Reg) != &AVR::PTRDISPREGSRegClass) { in SelectInlineAsmMemoryOperand()
277 Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass); in SelectInlineAsmMemoryOperand()
306 Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass); in SelectInlineAsmMemoryOperand()
326 CurDAG->SelectNodeTo(N, AVR::FRMIDX, getTargetLowering()->getPointerTy(DL), in select()
345 if (!RN || (RN->getReg() != AVR::SP)) { in select()
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H A DAVRRegisterInfo.td1 //===-- AVRRegisterInfo.td - AVR Register defs -------------*- tablegen -*-===//
10 // Declarations that describe the AVR register file
19 let Namespace = "AVR";
25 let Namespace = "AVR" in {
30 let Namespace = "AVR" in { def ptr : RegAltNameIndex; }
114 def GPR8 : RegisterClass<"AVR", [i8], 8,
125 def GPR8lo : RegisterClass<"AVR", [i8], 8,
130 def LD8 : RegisterClass<"AVR", [i8], 8,
140 def LD8lo : RegisterClass<"AVR", [i8], 8,
144 def DREGS : RegisterClass<"AVR", [i16], 8,
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H A DAVR.td1 //===-- AVR.td - Describe the AVR Target Machine ----------*- tablegen -*-===//
8 // This is the top level entry point for the AVR target.
18 // AVR Device Definitions
73 def AVR : Target {
H A DAVRSubtarget.h92 return hasTinyEncoding() ? AVR::R16 : AVR::R0; in getTmpRegister()
95 return hasTinyEncoding() ? AVR::R17 : AVR::R1; in getZeroRegister()
H A DREADME.md1 # AVR backend
3 This experimental backend is for the 8-bit Atmel [AVR](https://en.wikipedia.org/wiki/Atmel_AVR) mic…
7 * [Unresolved bugs](https://llvm.org/bugs/buglist.cgi?product=libraries&component=Backend%3A%20AVR&…
H A DAVRCallingConv.td1 //===-- AVRCallingConv.td - Calling Conventions for AVR ----*- tablegen -*-===//
8 // This describes the calling conventions for AVR architecture.
13 // AVR Return Value Calling Convention
23 // AVR Argument Calling Conventions
H A DAVRAsmPrinter.cpp138 Reg = TRI.getSubReg(Reg, (ByteNumber % BytesPerReg) ? AVR::sub_hi in PrintAsmOperand()
139 : AVR::sub_lo); in PrintAsmOperand()
168 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) { in PrintAsmMemoryOperand()
170 } else if (MI->getOperand(OpNum).getReg() == AVR::R29R28) { in PrintAsmMemoryOperand()
172 } else if (MI->getOperand(OpNum).getReg() == AVR::R27R26) { in PrintAsmMemoryOperand()
184 assert(MI->getOperand(OpNum).getReg() != AVR::R27R26 && in PrintAsmMemoryOperand()
207 bool IsProgMem = GV->getAddressSpace() == AVR::ProgramMemory; in lowerConstant()
H A DAVRInstrFormats.td1 //===-- AVRInstrInfo.td - AVR Instruction Formats ----------*- tablegen -*-===//
9 // AVR Instruction Format Definitions.
13 // A generic AVR instruction.
16 let Namespace = "AVR";
26 /// A 16-bit AVR instruction.
34 /// a 32-bit AVR instruction.
43 // Pseudo instructions are not real AVR instructions. The DAG stores
44 // pseudo instructions which are replaced by real AVR instructions by
/src/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp63 AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6,
64 AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,
65 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
66 AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
67 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
199 Inst.addOperand(MCOperand::createReg(AVR::R31R30)); in decodeFLPMX()
271 MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30)); in decodeMemri()
283 Inst.setOpcode(AVR::RJMPk); in decodeFBRk()
286 Inst.setOpcode(AVR::RCALLk); in decodeFBRk()
302 {0x000, AVR::BRLOk}, {0x400, AVR::BRSHk}, {0x001, AVR::BREQk}, in decodeCondBranch()
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/src/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp82 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) { in toDREG()
83 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; in toDREG()
358 if (RegNum == AVR::NoRegister) { in parseRegisterName()
361 if (RegNum == AVR::NoRegister) { in parseRegisterName()
371 if (RegNum == AVR::NoRegister) in parseRegisterName()
378 int RegNum = AVR::NoRegister; in parseRegister()
392 if (RegNum == AVR::NoRegister && RestoreOnFailure) { in parseRegister()
406 if (RegNo == AVR::NoRegister) in tryParseRegisterOperand()
410 if (AVR::R0 <= RegNo && RegNo <= AVR::R15 && in tryParseRegisterOperand()
411 STI.hasFeature(AVR::FeatureTinyEncoding)) in tryParseRegisterOperand()
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/src/contrib/llvm-project/lld/ELF/Arch/
H A DAVR.cpp44 class AVR final : public TargetInfo { class
46 AVR() { needsThunks = true; } in AVR() function in __anon1c62a49c0111::AVR
58 RelExpr AVR::getRelExpr(RelType type, const Symbol &s, in getRelExpr()
106 bool AVR::needsThunk(RelExpr expr, RelType type, const InputFile *file, in needsThunk()
119 void AVR::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { in relocate()
271 static AVR target; in getAVRTargetInfo()
279 uint32_t AVR::calcEFlags() const { in calcEFlags()
/src/sys/contrib/device-tree/Bindings/powerpc/4xx/
H A Dakebono.txt44 1.d) The AVR node
46 The Akebono board has an Atmel AVR microprocessor attached to the I2C
52 - reg : should contain the I2C bus address for the AVR.

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