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Searched refs:APLL (Results 1 – 9 of 9) sorted by relevance

/src/sys/contrib/device-tree/Bindings/clock/ti/
H A Dapll.txt1 Binding for Texas Instruments APLL clock.
4 register-mapped APLL with usually two selectable input clocks
8 modes (locked, low power stop etc.) APLL mostly behaves like
18 - reg : address and length of the register set for controlling the APLL.
/src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h27 #define APLL 18 macro
H A Dxlnx-zynqmp-clk.h21 #define APLL 2 macro
H A Dnuvoton,ma35d1-clk.h22 #define APLL 11 macro
/src/sys/contrib/device-tree/src/arm64/xilinx/
H A Dxlnx-zynqmp-clk.h14 #define APLL 2 macro
/src/sys/contrib/device-tree/src/arm64/nuvoton/
H A Dma35d1-som-256m.dts43 <&clk APLL>,
H A Dma35d1-iot-512m.dts43 <&clk APLL>,
/src/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dcp110-system-controller.txt35 - 0 0 APLL
/src/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3036.dtsi242 * Fix the emac parent clock is DPLL instead of APLL.