1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005, Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Machine dependent interfaces */ 30 31 #ifndef _DEV_HWPMC_AMD_H_ 32 #define _DEV_HWPMC_AMD_H_ 1 33 34 /* CPUIDs */ 35 #define CPUID_EXTPERFMON 0x80000022 36 #define EXTPERFMON_CORE_PMCS(x) ((x) & 0x0F) 37 #define EXTPERFMON_DF_PMCS(x) (((x) >> 10) & 0x3F) 38 39 /* AMD K8 PMCs */ 40 #define AMD_PMC_EVSEL_0 0xC0010000 41 #define AMD_PMC_EVSEL_1 0xC0010001 42 #define AMD_PMC_EVSEL_2 0xC0010002 43 #define AMD_PMC_EVSEL_3 0xC0010003 44 45 #define AMD_PMC_PERFCTR_0 0xC0010004 46 #define AMD_PMC_PERFCTR_1 0xC0010005 47 #define AMD_PMC_PERFCTR_2 0xC0010006 48 #define AMD_PMC_PERFCTR_3 0xC0010007 49 50 /* 51 * For older AMD processors we have hard coded the original four core counters. 52 * For newer processors we use the cpuid bits to setup the counter table. The 53 * counts below are the default number of registers assuming that you do not 54 * have CPUID leaf 0x80000022. The maximum number of counters is computed 55 * based on the available bits in the CPUID leaf and reserved MSR space. 56 * 57 * Refer to the PPRs for AMD Family 1Ah. 58 */ 59 60 /* CORE */ 61 #define AMD_PMC_CORE_BASE 0xC0010200 62 #define AMD_PMC_CORE_DEFAULT 6 63 #define AMD_PMC_CORE_MAX 16 64 65 #define AMD_PMC_COUNTERMASK 0xFF000000 66 #define AMD_PMC_PRECISERETIRE (1ULL << 43) /* Only valid for PERF_CTL2 */ 67 #define AMD_PMC_HOST (1ULL << 41) 68 #define AMD_PMC_GUEST (1ULL << 40) 69 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 70 #define AMD_PMC_INVERT (1 << 23) 71 #define AMD_PMC_ENABLE (1 << 22) 72 #define AMD_PMC_INT (1 << 20) 73 #define AMD_PMC_PC (1 << 19) 74 #define AMD_PMC_EDGE (1 << 18) 75 #define AMD_PMC_OS (1 << 17) 76 #define AMD_PMC_USR (1 << 16) 77 78 #define AMD_PMC_UNITMASK 0xFF00 79 #define AMD_PMC_EVENTMASK 0xF000000FF 80 81 #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 82 #define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24)) 83 84 #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 85 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 86 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 87 88 #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 89 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 90 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 91 92 /* L3 */ 93 #define AMD_PMC_L3_BASE 0xC0010230 94 #define AMD_PMC_L3_DEFAULT 6 95 #define AMD_PMC_L3_MAX 6 96 97 /* 98 * L3 counters change their encoding slightly between Family 17h and Family 19h 99 * processors. 100 * 101 * Refer to the following documents for the L3 fields: 102 * PPR for AMD Family 17h Model 20h A1 55772-A1 Rev. 3.08 April 14, 2021 103 * PPR for AMD Family 19h Model 51h A1 56569-A1 Rev. 3.03 September 21, 2021 104 * PPR for AMD Family 1Ah Model 02h C1 57238 Rev. 0.24 September 29, 2024 105 */ 106 #define AMD_PMC_L31_SLICEMASK (0x000F000000000000ULL) 107 #define AMD_PMC_L31_COREMASK (0xFF00000000000000ULL) 108 109 #define AMD_PMC_L31_TO_SLICE(x) (((uint64_t)(x) << 48) & AMD_PMC_L31_SLICEMASK) 110 #define AMD_PMC_L31_TO_CORE(x) (((uint64_t)(x) << 56) & AMD_PMC_L31_COREMASK) 111 112 #define AMD_PMC_L32_THREADMASK (0x0F00000000000000ULL) 113 #define AMD_PMC_L32_SOURCEMASK (0x0007000000000000ULL) 114 #define AMD_PMC_L32_ALLCORES (1ULL << 47) 115 #define AMD_PMC_L32_ALLSOURCES (1ULL << 46) 116 #define AMD_PMC_L32_COREMASK (0x00001C0000000000ULL) 117 118 #define AMD_PMC_L32_TO_THREAD(x) (((uint64_t)(x) << 56) & AMD_PMC_L32_THREADMASK) 119 #define AMD_PMC_L32_TO_SOURCEID(x) (((uint64_t)(x) << 48) & AMD_PMC_L32_SOURCEMASK) 120 #define AMD_PMC_L32_TO_COREID(x) (((uint64_t)(x) << 42) & AMD_PMC_L32_COREMASK) 121 122 #define AMD_PMC_L3_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 123 #define AMD_PMC_L3_TO_EVENTMASK(x) ((x) & 0xFF) 124 125 #define AMD_PMC_L3_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 126 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 127 128 /* DF */ 129 #define AMD_PMC_DF_BASE 0xC0010240 130 #define AMD_PMC_DF_DEFAULT 4 131 #define AMD_PMC_DF_MAX 64 132 133 #define AMD_PMC_DF_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 134 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 135 136 /* 137 * DF counters change their encoding between Family 19h and Family 1Ah 138 * processors. 139 * 140 * Refer to the same documents as the L3 counters. 141 */ 142 #define AMD_PMC_DF1_TO_EVENTMASK(x) (((x) & 0xFF) | \ 143 (((uint64_t)(x) & 0x0F00) << 24) | (((uint64_t)(x) & 0x3000) << 47)) 144 #define AMD_PMC_DF1_TO_UNITMASK(x) (((x) & 0xFF) << 8) 145 146 #define AMD_PMC_DF2_TO_EVENTMASK(x) (((x) & 0xFF) | \ 147 (((uint64_t)(x) & 0x7F00) << 24)) 148 #define AMD_PMC_DF2_TO_UNITMASK(x) ((((x) & 0xFF) << 8) | \ 149 (((uint64_t)(x) & 0x0F00) << 16)) 150 151 #define AMD_NPMCS_K8 4 152 #define AMD_NPMCS_MAX (AMD_PMC_CORE_MAX + AMD_PMC_L3_MAX + \ 153 AMD_PMC_DF_MAX) 154 155 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 156 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 157 158 #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 159 #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 160 161 enum sub_class { 162 PMC_AMD_SUB_CLASS_CORE, 163 PMC_AMD_SUB_CLASS_L3_CACHE, 164 PMC_AMD_SUB_CLASS_DATA_FABRIC 165 }; 166 167 struct pmc_md_amd_op_pmcallocate { 168 uint64_t pm_amd_config; 169 uint32_t pm_amd_sub_class; 170 }; 171 172 #ifdef _KERNEL 173 174 /* MD extension for 'struct pmc' */ 175 struct pmc_md_amd_pmc { 176 uint64_t pm_amd_evsel; 177 }; 178 179 #endif /* _KERNEL */ 180 #endif /* _DEV_HWPMC_AMD_H_ */ 181