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Searched refs:xive_set_field32 (Results 1 – 6 of 6) sorted by relevance

/qemu/tests/qtest/
H A Dpnv-xive2-common.c102 nvp.w0 = xive_set_field32(NVP2_W0_VALID, 0, 1); in set_nvp()
103 nvp.w0 = xive_set_field32(NVP2_W0_PGOFIRST, nvp.w0, first); in set_nvp()
104 nvp.w6 = xive_set_field32(NVP2_W6_REPORTING_LINE, nvp.w6, in set_nvp()
106 nvp.w7 = xive_set_field32(NVP2_W7_REPORTING_LINE, nvp.w7, in set_nvp()
138 nvg.w0 = xive_set_field32(NVGC2_W0_VALID, 0, 1); in set_nvg()
139 nvg.w0 = xive_set_field32(NVGC2_W0_PGONEXT, nvg.w0, next); in set_nvg()
172 end.w0 = xive_set_field32(END2_W0_VALID, 0, 1); in set_end()
173 end.w0 = xive_set_field32(END2_W0_ENQUEUE, end.w0, 1); in set_end()
174 end.w0 = xive_set_field32(END2_W0_UCOND_NOTIFY, end.w0, 1); in set_end()
175 end.w0 = xive_set_field32(END2_W0_BACKLOG, end.w0, 1); in set_end()
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/qemu/hw/intc/
H A Dxive2.c170 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); in xive2_presenter_nvp_backlog_op()
362 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); in xive2_end_enqueue()
365 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); in xive2_end_enqueue()
367 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); in xive2_end_enqueue()
535 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); in xive2_tctx_save_ctx()
536 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); in xive2_tctx_save_ctx()
542 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); in xive2_tctx_save_ctx()
545 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); in xive2_tctx_save_ctx()
548 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); in xive2_tctx_save_ctx()
552 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); in xive2_tctx_save_ctx()
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H A Dxive.c215 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); in xive_tm_pull_pool_ctx()
462 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); in xive_tm_pull_os_ctx()
489 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); in xive_tctx_need_resend()
1534 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); in xive_end_enqueue()
1536 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); in xive_end_enqueue()
1858 end->w1 = xive_set_field32(end_esmask, end->w1, pq); in xive_router_end_es_notify()
1993 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); in xive_router_end_notify()
2193 end.w1 = xive_set_field32(end_esmask, end.w1, pq); in xive_end_source_read()
H A Dspapr_xive.c1380 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); in h_int_set_queue_config()
1420 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | in h_int_set_queue_config()
1421 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); in h_int_set_queue_config()
1422 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); in h_int_set_queue_config()
1435 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); in h_int_set_queue_config()
H A Dspapr_xive_kvm.c400 end->w1 = xive_set_field32(END_W1_GENERATION, 0ul, kvm_eq.qtoggle) | in kvmppc_xive_get_queue_config()
401 xive_set_field32(END_W1_PAGE_OFF, 0ul, kvm_eq.qindex); in kvmppc_xive_get_queue_config()
/qemu/include/hw/ppc/
H A Dxive_regs.h216 static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word, in xive_set_field32() function