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Searched refs:writel (Results 1 – 17 of 17) sorted by relevance

/qemu/tests/qtest/
H A Dnpcm7xx_gpio-test.c59 writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248); in gpio_unlock()
60 writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73); in gpio_unlock()
69 writel(GPIO(n) + GP_N_EVEN, 0x00000000); in gpio_reset()
70 writel(GPIO(n) + GP_N_EVST, 0xffffffff); in gpio_reset()
71 writel(GPIO(n) + GP_N_POL, 0x00000000); in gpio_reset()
72 writel(GPIO(n) + GP_N_DOUT, 0x00000000); in gpio_reset()
73 writel(GPIO(n) + GP_N_OE, 0x00000000); in gpio_reset()
74 writel(GPIO(n) + GP_N_OTYP, 0x00000000); in gpio_reset()
75 writel(GPIO(n) + GP_N_PU, 0xffffffff); in gpio_reset()
76 writel(GPIO(n) + GP_N_PD, 0x00000000); in gpio_reset()
[all …]
H A Dsse-timer-test.c72 writel(COUNTER_BASE + CNTCR, 0); in reset_counter_and_timer()
73 writel(TIMER_BASE + CNTP_CTL, 0); in reset_counter_and_timer()
74 writel(TIMER_BASE + CNTP_AIVAL_CTL, 0); in reset_counter_and_timer()
75 writel(COUNTER_BASE + CNTCV_LO, 0); in reset_counter_and_timer()
76 writel(COUNTER_BASE + CNTCV_HI, 0); in reset_counter_and_timer()
89 writel(COUNTER_BASE + CNTCR, 1); in test_counter()
94 writel(COUNTER_BASE + CNTCR, 0); in test_counter()
95 writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */ in test_counter()
96 writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */ in test_counter()
113 writel(PERIPHNSPPC0, 1); in test_timer()
[all …]
H A Dbcm2835-i2c-test.c44 writel(base_addr + BCM2835_I2C_C, in bcm2835_i2c_init_transfer()
56 writel(base_addr + BCM2835_I2C_A, 0x50); in test_i2c_read_write()
57 writel(base_addr + BCM2835_I2C_DLEN, 3); in test_i2c_read_write()
61 writel(base_addr + BCM2835_I2C_FIFO, TMP105_REG_T_HIGH); in test_i2c_read_write()
62 writel(base_addr + BCM2835_I2C_FIFO, 0xde); in test_i2c_read_write()
63 writel(base_addr + BCM2835_I2C_FIFO, 0xad); in test_i2c_read_write()
66 writel(base_addr + BCM2835_I2C_S, BCM2835_I2C_S_DONE | BCM2835_I2C_S_ERR | in test_i2c_read_write()
70 writel(base_addr + BCM2835_I2C_A, 0x50); in test_i2c_read_write()
71 writel(base_addr + BCM2835_I2C_DLEN, 1); in test_i2c_read_write()
75 writel(base_addr + BCM2835_I2C_FIFO, TMP105_REG_T_HIGH); in test_i2c_read_write()
[all …]
H A Dbcm2835-dma-test.c52 writel(RASPI3_IC_BASE + IRQ_ENABLE_1, 1 << gpu_irq_line); in bcm2835_dma_test_interrupt()
63 writel(SCB_ADDR + 0, BCM2708_DMA_S_INC | BCM2708_DMA_D_INC | in bcm2835_dma_test_interrupt()
65 writel(SCB_ADDR + 4, S_ADDR); /* source address */ in bcm2835_dma_test_interrupt()
66 writel(SCB_ADDR + 8, D_ADDR); /* destination address */ in bcm2835_dma_test_interrupt()
67 writel(SCB_ADDR + 12, TXFR_LEN); /* transfer length */ in bcm2835_dma_test_interrupt()
68 writel(dma_base + BCM2708_DMA_ADDR, SCB_ADDR); in bcm2835_dma_test_interrupt()
70 writel(S_ADDR, check_data); in bcm2835_dma_test_interrupt()
72 writel(word, ~check_data); in bcm2835_dma_test_interrupt()
75 writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_ACTIVE); in bcm2835_dma_test_interrupt()
96 writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_INT); in bcm2835_dma_test_interrupt()
H A Dcmsdk-apb-dualtimer-test.c53 writel(TIMER_BASE + TIMER1LOAD, 1000); in test_dualtimer()
55 writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); in test_dualtimer()
75 writel(TIMER_BASE + TIMER1INTCLR, 1); in test_dualtimer()
79 writel(TIMER_BASE + TIMER1CONTROL, 0); in test_dualtimer()
87 writel(TIMER_BASE + TIMER2LOAD, 1000); in test_prescale()
89 writel(TIMER_BASE + TIMER2CONTROL, in test_prescale()
107 writel(TIMER_BASE + TIMER2INTCLR, 1); in test_prescale()
111 writel(TIMER_BASE + TIMER2CONTROL, 0); in test_prescale()
H A Dcmsdk-apb-watchdog-test.c91 writel(wdog_base + WDOGCONTROL, 1); in test_watchdog()
92 writel(wdog_base + WDOGLOAD, 1000); in test_watchdog()
112 writel(wdog_base + WDOGINTCLR, 0); in test_watchdog()
137 writel(WDOG_BASE + WDOGCONTROL, 1); in test_clock_change()
138 writel(WDOG_BASE + WDOGLOAD, 1000); in test_clock_change()
149 writel(SSYS_BASE + RCC, rcc); in test_clock_change()
165 writel(WDOG_BASE + WDOGINTCLR, 0); in test_clock_change()
196 writel(wdog_base + WDOGLOAD, 3000); in test_watchdog_reset()
197 writel(wdog_base + WDOGCONTROL, 1); in test_watchdog_reset()
245 writel(wdog_base + WDOGLOAD, 4000); in test_watchdog_inten()
[all …]
H A Dcmsdk-apb-timer-test.c33 writel(TIMER_BASE + RELOAD, 1000); in test_timer()
34 writel(TIMER_BASE + CTRL, 9); in test_timer()
51 writel(TIMER_BASE + INTSTATUS, 0); in test_timer()
53 writel(TIMER_BASE + INTSTATUS, 1); in test_timer()
57 writel(TIMER_BASE + CTRL, 0); in test_timer()
H A Dstm32l4x5_rcc-test.c26 writel(NVIC_ISER, 1 << n); in enable_nvic_irq()
31 writel(NVIC_ICPR, 1 << n); in unpend_nvic_irq()
41 writel(RCC_BASE_ADDR + offset, value); in rcc_writel()
H A Dtpm-crb-test.c84 writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ, 1); in tpm_crb_test()
95 writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_START, start); in tpm_crb_test()
115 writel(TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ, 2); in tpm_crb_test()
123 writel(TPM_CRB_ADDR_BASE + A_CRB_LOC_CTRL, 2); in tpm_crb_test()
H A Dstm32l4x5_syscfg-test.c37 writel(SYSCFG_BASE_ADDR + offset, value); in syscfg_writel()
304 writel(RCC_APB2ENR, readl(RCC_APB2ENR) | (0x1 << 0)); in test_clock_enable()
H A Dstm32l4x5_exti-test.c39 writel(NVIC_ISER, 1 << n); in enable_nvic_irq()
44 writel(NVIC_ICPR, 1 << n); in unpend_nvic_irq()
54 writel(EXTI_BASE_ADDR + offset, value); in exti_writel()
H A Dtest-arm-mptimer.c40 writel(TIMER_BASE_PHYS + TIMER_LOAD, load); in timer_load()
51 writel(TIMER_BASE_PHYS + TIMER_CONTROL, ctl); in timer_start()
56 writel(TIMER_BASE_PHYS + TIMER_CONTROL, 0); in timer_stop()
61 writel(TIMER_BASE_PHYS + TIMER_INTSTAT, 1); in timer_int_clr()
89 writel(TIMER_BASE_PHYS + TIMER_COUNTER, value); in timer_set_counter()
H A Dnpcm7xx_timer-test.c129 writel(td->tim->base_addr + offset, value); in tim_write()
182 writel(timer_block[i].base_addr + timer[j].tcsr_offset, in tim_reset()
185 writel(timer_block[i].base_addr + TISR, -1); in tim_reset()
H A Dlibqtest-single.h199 static inline void writel(uint64_t addr, uint32_t value) in writel() function
H A Dstm32l4x5_gpio-test.c101 writel(gpio + offset, value); in gpio_writel()
515 writel(RCC_AHB2ENR, readl(RCC_AHB2ENR) | (0x1 << gpio_id)); in test_clock_enable()
H A Dxlnx-versal-trng-test.c123 writel(TRNG_BASEADDR + ra, val); in trng_write()
H A Dtpm-tis-util.c399 writel(TIS_REG(0, TPM_TIS_REG_STS), TPM_TIS_STS_COMMAND_READY); in tpm_tis_test_check_transmit()