| /qemu/tests/qtest/ |
| H A D | pnv-xive2-common.c | 104 nvp.w6 = xive_set_field32(NVP2_W6_REPORTING_LINE, nvp.w6, in set_nvp()
113 uint64_t upper = xive_get_field32(0x0fffffff, nvp->w6); in get_cl_pair_addr()
184 end.w6 = xive_set_field32(END2_W6_IGNORE, 0, i); in set_end()
185 end.w6 = xive_set_field32(END2_W6_VP_OFFSET, end.w6, nvp_index); in set_end()
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| /qemu/tests/tcg/multiarch/ |
| H A D | sha512.c | 274 uint64_t w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15; in Transform() local
282 Round(c, d, e, &f, g, h, a, &b, 0x923f82a4af194f9bull, w6 = be64_to_cpu(chunk[6])); in Transform()
298 Round(d, e, f, &g, h, a, b, &c, 0x4a7484aa6ea6e483ull, w5 += sigma1(w3) + w14 + sigma0(w6)); in Transform()
299 Round(c, d, e, &f, g, h, a, &b, 0x5cb0a9dcbd41fbd4ull, w6 += sigma1(w4) + w15 + sigma0(w7)); in Transform()
301 Round(a, b, c, &d, e, f, g, &h, 0x983e5152ee66dfabull, w8 += sigma1(w6) + w1 + sigma0(w9)); in Transform()
306 Round(d, e, f, &g, h, a, b, &c, 0xd5a79147930aa725ull, w13 += sigma1(w11) + w6 + sigma0(w14)); in Transform()
315 Round(d, e, f, &g, h, a, b, &c, 0x766a0abb3c77b2a8ull, w5 += sigma1(w3) + w14 + sigma0(w6)); in Transform()
316 Round(c, d, e, &f, g, h, a, &b, 0x81c2c92e47edaee6ull, w6 += sigma1(w4) + w15 + sigma0(w7)); in Transform()
318 Round(a, b, c, &d, e, f, g, &h, 0xa2bfe8a14cf10364ull, w8 += sigma1(w6) + w1 + sigma0(w9)); in Transform()
323 Round(d, e, f, &g, h, a, b, &c, 0xd69906245565a910ull, w13 += sigma1(w11) + w6 + sigma0(w14)); in Transform()
[all …]
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| /qemu/include/hw/ppc/ |
| H A D | xive2_regs.h | 98 uint32_t w6; member
131 (be32_to_cpu((end)->w6) & END2_W6_IGNORE)
133 (be32_to_cpu((end)->w6) & END2_W6_CROWD)
180 uint32_t w6; member
227 uint32_t w6; member
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| H A D | xive_regs.h | 260 uint32_t w6; member
306 uint32_t w6; member
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| /qemu/hw/intc/ |
| H A D | xive2.c | 40 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | in xive2_nvp_reporting_addr()
229 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); in xive2_end_pic_print_info()
230 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); in xive2_end_pic_print_info()
1374 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); in xive2_router_end_notify()
1397 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); in xive2_router_end_notify()
1398 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); in xive2_router_end_notify()
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| H A D | spapr_xive.c | 140 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); in spapr_xive_end_pic_print_info()
532 VMSTATE_UINT32(w6, XiveEND),
1196 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); in h_int_get_source_config()
1197 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); in h_int_get_source_config()
1420 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | in h_int_set_queue_config()
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| H A D | xive.c | 1479 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); in xive_end_pic_print_info()
1480 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); in xive_end_pic_print_info()
1920 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); in xive_router_end_notify()
1943 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); in xive_router_end_notify()
1944 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); in xive_router_end_notify()
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| /qemu/tests/tcg/mips/include/ |
| H A D | wrappers_msa.h | 44 RESET_MSA_REGISTER(w6); in reset_msa_registers()
|