/qemu/hw/intc/ |
H A D | xive2.c | 60 ptr = (uint8_t *)&nvgc->w2 + priority * 3; in xive2_nvgc_get_backlog() 84 ptr = (uint8_t *)&nvgc->w2 + priority * 3; in xive2_nvgc_set_backlog() 156 old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); in xive2_presenter_nvp_backlog_op() 170 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); in xive2_presenter_nvp_backlog_op() 304 xive_get_field32(NVP2_W2_IPB, nvp->w2), in xive2_nvp_pic_print_info() 315 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); in xive2_nvp_pic_print_info() 535 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); in xive2_tctx_save_ctx() 536 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); in xive2_tctx_save_ctx() 542 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); in xive2_tctx_save_ctx() 545 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); in xive2_tctx_save_ctx() [all …]
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H A D | spapr_xive.c | 528 VMSTATE_UINT32(w2, XiveEND), 1377 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); in h_int_set_queue_config()
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H A D | xive.c | 757 uint32_t w2 = xive_tctx_word2(ring); in xive_tctx_ring_print() local 763 be32_to_cpu(w2)); in xive_tctx_ring_print()
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/qemu/tests/tcg/multiarch/ |
H A D | sha512.c | 274 uint64_t w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15; in Transform() local 278 Round(g, h, a, &b, c, d, e, &f, 0xb5c0fbcfec4d3b2full, w2 = be64_to_cpu(chunk[2])); in Transform() 294 Round(h, a, b, &c, d, e, f, &g, 0xefbe4786384f25e3ull, w1 += sigma1(w15) + w10 + sigma0(w2)); in Transform() 295 Round(g, h, a, &b, c, d, e, &f, 0x0fc19dc68b8cd5b5ull, w2 += sigma1(w0) + w11 + sigma0(w3)); in Transform() 297 Round(e, f, g, &h, a, b, c, &d, 0x2de92c6f592b0275ull, w4 += sigma1(w2) + w13 + sigma0(w5)); in Transform() 302 Round(h, a, b, &c, d, e, f, &g, 0xa831c66d2db43210ull, w9 += sigma1(w7) + w2 + sigma0(w10)); in Transform() 311 Round(h, a, b, &c, d, e, f, &g, 0x2e1b21385c26c926ull, w1 += sigma1(w15) + w10 + sigma0(w2)); in Transform() 312 Round(g, h, a, &b, c, d, e, &f, 0x4d2c6dfc5ac42aedull, w2 += sigma1(w0) + w11 + sigma0(w3)); in Transform() 314 Round(e, f, g, &h, a, b, c, &d, 0x650a73548baf63deull, w4 += sigma1(w2) + w13 + sigma0(w5)); in Transform() 319 Round(h, a, b, &c, d, e, f, &g, 0xa81a664bbc423001ull, w9 += sigma1(w7) + w2 + sigma0(w10)); in Transform() [all …]
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/qemu/include/hw/ppc/ |
H A D | xive2_regs.h | 85 uint32_t w2; member 137 return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 | in xive2_end_qaddr() 164 uint32_t w2; member 223 uint32_t w2; member
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H A D | xive_regs.h | 250 uint32_t w2; member 286 return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 | in xive_end_qaddr() 301 uint32_t w2; member
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/qemu/crypto/ |
H A D | aes.c | 1066 uint32_t w0, w1, w2, w3; in aesenc_SB_SR_MC_AK_swap() local 1078 w2 = (AES_Te0[st->b[swap_b ^ AES_SH(0x8)]] ^ in aesenc_SB_SR_MC_AK_swap() 1092 w2 = bswap32(w2); in aesenc_SB_SR_MC_AK_swap() 1098 r->w[swap_w ^ 2] = rk->w[swap_w ^ 2] ^ w2; in aesenc_SB_SR_MC_AK_swap() 1228 uint32_t w0, w1, w2, w3; in aesdec_ISB_ISR_IMC_AK_swap() local 1240 w2 = (AES_Td0[st->b[swap_b ^ AES_ISH(0x8)]] ^ in aesdec_ISB_ISR_IMC_AK_swap() 1254 w2 = bswap32(w2); in aesdec_ISB_ISR_IMC_AK_swap() 1260 r->w[swap_w ^ 2] = rk->w[swap_w ^ 2] ^ w2; in aesdec_ISB_ISR_IMC_AK_swap()
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/qemu/hw/i386/kvm/ |
H A D | xenstore_impl.c | 1314 XsWatch *w2, *w, **l; in xs_impl_reset_watches() local 1323 w = w2 = w1; in xs_impl_reset_watches() 1328 if (w2 == w) { in xs_impl_reset_watches() 1329 w2 = w->next; in xs_impl_reset_watches() 1341 if (w1 != w2) { in xs_impl_reset_watches() 1351 if (w2) { in xs_impl_reset_watches() 1352 g_hash_table_insert(s->watches, watch_paths[i], w2); in xs_impl_reset_watches()
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/qemu/include/libdecnumber/ |
H A D | decNumberLocal.h | 117 uInt u0, u1, v0, v1, w0, w1, w2, t; \ 122 w1=t & 0xffff; w2=t>>16; \ 124 (w)=u1*v1 + w2 + (w1>>16);}
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/qemu/tests/qtest/ |
H A D | pnv-xive2-common.c | 179 end.w2 = cpu_to_be32(queue_hi); in set_end()
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/qemu/tests/tcg/mips/include/ |
H A D | wrappers_msa.h | 40 RESET_MSA_REGISTER(w2); in reset_msa_registers()
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