| /qemu/hw/pci/ |
| H A D | shpc.c | 455 uint8_t w1cmask = shpc->w1cmask[a]; in shpc_write() local
456 assert(!(wmask & w1cmask)); in shpc_write()
458 shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ in shpc_write()
671 shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d)); in shpc_init()
685 pci_set_long(shpc->w1cmask + SHPC_SERR_INT, in shpc_init()
698 pci_set_byte(shpc->w1cmask + in shpc_init()
742 g_free(shpc->w1cmask); in shpc_free()
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| H A D | pci.c | 546 pci_get_word(dev->w1cmask + PCI_COMMAND)); in pci_do_device_reset()
549 pci_get_word(dev->w1cmask + PCI_STATUS)); in pci_do_device_reset()
553 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); in pci_do_device_reset()
797 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { in get_pci_config_device()
801 s->cmask[i], s->wmask[i], s->w1cmask[i]); in get_pci_config_device()
1042 pci_set_word(dev->w1cmask + PCI_STATUS, in pci_init_w1cmask()
1095 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, in pci_init_mask_bridge()
1165 pci_dev->w1cmask = g_malloc0(config_size); in pci_config_alloc()
1174 g_free(pci_dev->w1cmask); in pci_config_free()
1777 uint8_t w1cmask = d->w1cmask[addr + i]; in pci_default_write_config() local
[all …]
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| H A D | pcie_aer.c | 113 pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, in pcie_aer_init()
128 pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS, in pcie_aer_init()
159 pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS, in pcie_aer_init()
750 pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS, in pcie_aer_root_init()
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| H A D | pcie.c | 369 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, in pcie_cap_deverr_init()
725 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, in pcie_cap_slot_init()
1083 memset(dev->w1cmask + offset, 0, size); in pcie_add_capability()
1263 pci_set_word(dev->w1cmask + offset + PCI_PRI_STATUS, status_reg_rw1_mask); in pcie_pri_init()
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| /qemu/hw/i386/ |
| H A D | amd_iommu.c | 92 uint64_t romask, uint64_t w1cmask) in amdvi_set_quad() argument
96 stq_le_p(&s->w1cmask[addr], w1cmask); in amdvi_set_quad()
124 uint16_t w1cmask = lduw_le_p(&s->w1cmask[addr]); in amdvi_writew() local
127 ((oldval & romask) | (val & ~romask)) & ~(val & w1cmask)); in amdvi_writew()
133 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); in amdvi_writel() local
136 ((oldval & romask) | (val & ~romask)) & ~(val & w1cmask)); in amdvi_writel()
142 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); in amdvi_writeq() local
145 ((oldval & romask) | (val & ~romask)) & ~(val & w1cmask)); in amdvi_writeq()
1647 VMSTATE_UINT8_ARRAY(w1cmask, AMDVIState, AMDVI_MMIO_SIZE),
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| H A D | amd_iommu.h | 362 uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */ member
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| H A D | intel_iommu.c | 96 uint64_t wmask, uint64_t w1cmask) in vtd_define_quad() argument
100 stq_le_p(&s->w1cmask[addr], w1cmask); in vtd_define_quad()
109 uint32_t wmask, uint32_t w1cmask) in vtd_define_long() argument
113 stl_le_p(&s->w1cmask[addr], w1cmask); in vtd_define_long()
126 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); in vtd_set_quad() local
128 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); in vtd_set_quad()
135 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); in vtd_set_long() local
137 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); in vtd_set_long()
4604 memset(s->w1cmask, 0, DMAR_REG_SIZE); in vtd_init()
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| /qemu/hw/ide/ |
| H A D | cmd646.c | 267 dev->w1cmask[CFR] = CFR_INTR_CH0; in pci_cmd646_ide_realize()
269 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1; in pci_cmd646_ide_realize()
271 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; in pci_cmd646_ide_realize()
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| /qemu/include/hw/pci/ |
| H A D | shpc.h | 27 uint8_t *w1cmask; member
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| H A D | pci_device.h | 77 uint8_t *w1cmask; member
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| /qemu/include/hw/i386/ |
| H A D | intel_iommu.h | 261 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ member
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| /qemu/hw/net/ |
| H A D | igb.c | 375 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, in igb_add_pm_capability()
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| H A D | e1000e.c | 391 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, in e1000e_add_pm_capability()
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| /qemu/docs/devel/migration/ |
| H A D | compatibility.rst | 365 pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
418 pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
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