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Searched refs:w0 (Results 1 – 14 of 14) sorted by relevance

/qemu/include/hw/ppc/
H A Dxive2_regs.h59 uint32_t w0; member
111 #define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
112 #define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
114 (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
115 #define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
117 (be32_to_cpu((end)->w0) & END2_W0_PRECL_ESC_CTL)
119 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
121 (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
123 (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
125 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
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H A Dxive_regs.h226 uint32_t w0; member
272 #define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID)
273 #define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
274 #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
275 #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
276 #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
278 (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
280 (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
282 (be32_to_cpu((end)->w0) & END_W0_FIRMWARE)
296 uint32_t w0; member
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/qemu/tests/qtest/
H A Dpnv-xive2-common.c102 nvp.w0 = xive_set_field32(NVP2_W0_VALID, 0, 1); in set_nvp()
103 nvp.w0 = xive_set_field32(NVP2_W0_PGOFIRST, nvp.w0, first); in set_nvp()
138 nvg.w0 = xive_set_field32(NVGC2_W0_VALID, 0, 1); in set_nvg()
139 nvg.w0 = xive_set_field32(NVGC2_W0_PGONEXT, nvg.w0, next); in set_nvg()
172 end.w0 = xive_set_field32(END2_W0_VALID, 0, 1); in set_end()
173 end.w0 = xive_set_field32(END2_W0_ENQUEUE, end.w0, 1); in set_end()
174 end.w0 = xive_set_field32(END2_W0_UCOND_NOTIFY, end.w0, 1); in set_end()
175 end.w0 = xive_set_field32(END2_W0_BACKLOG, end.w0, 1); in set_end()
/qemu/hw/nvram/
H A Dxlnx-versal-efuse-cache.c36 unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32); in efuse_cache_read() local
41 assert(w0 == w1 || (w0 + 32) == w1); in efuse_cache_read()
44 if (w0 < w1) { in efuse_cache_read()
46 ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL); in efuse_cache_read()
/qemu/common-user/host/aarch64/
H A Dsafe-syscall.inc.S79 0: neg w0, w0
84 2: mov w0, #QEMU_ERESTARTSYS
/qemu/tests/tcg/multiarch/
H A Dsha512.c274 uint64_t w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15; in Transform() local
276 Round(a, b, c, &d, e, f, g, &h, 0x428a2f98d728ae22ull, w0 = be64_to_cpu(chunk[0])); in Transform()
293 Round(a, b, c, &d, e, f, g, &h, 0xe49b69c19ef14ad2ull, w0 += sigma1(w14) + w9 + sigma0(w1)); in Transform()
295 Round(g, h, a, &b, c, d, e, &f, 0x0fc19dc68b8cd5b5ull, w2 += sigma1(w0) + w11 + sigma0(w3)); in Transform()
300 Round(b, c, d, &e, f, g, h, &a, 0x76f988da831153b5ull, w7 += sigma1(w5) + w0 + sigma0(w8)); in Transform()
308 Round(b, c, d, &e, f, g, h, &a, 0x142929670a0e6e70ull, w15 += sigma1(w13) + w8 + sigma0(w0)); in Transform()
310 Round(a, b, c, &d, e, f, g, &h, 0x27b70a8546d22ffcull, w0 += sigma1(w14) + w9 + sigma0(w1)); in Transform()
312 Round(g, h, a, &b, c, d, e, &f, 0x4d2c6dfc5ac42aedull, w2 += sigma1(w0) + w11 + sigma0(w3)); in Transform()
317 Round(b, c, d, &e, f, g, h, &a, 0x92722c851482353bull, w7 += sigma1(w5) + w0 + sigma0(w8)); in Transform()
325 Round(b, c, d, &e, f, g, h, &a, 0x106aa07032bbd1b8ull, w15 += sigma1(w13) + w8 + sigma0(w0)); in Transform()
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/qemu/hw/intc/
H A Dspapr_xive.c138 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in spapr_xive_end_pic_print_info()
415 nvt->w0 = cpu_to_be32(NVT_W0_VALID); in spapr_xive_get_nvt()
526 VMSTATE_UINT32(w0, XiveEND),
1278 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; in h_int_get_queue_info()
1379 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); in h_int_set_queue_config()
1380 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); in h_int_set_queue_config()
1425 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); in h_int_set_queue_config()
1427 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); in h_int_set_queue_config()
1436 end.w0 |= cpu_to_be32(END_W0_VALID); in h_int_set_queue_config()
1541 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; in h_int_get_queue_config()
H A Dxive2.c305 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); in xive2_nvp_pic_print_info()
333 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); in xive2_nvgc_pic_print_info()
439 current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F; in xive2_presenter_backlog_scan()
537 if (nvp.w0 & NVP2_W0_L) { in xive2_tctx_save_ctx()
544 if (nvp.w0 & NVP2_W0_G) { in xive2_tctx_save_ctx()
547 if (nvp.w0 & NVP2_W0_T) { in xive2_tctx_save_ctx()
829 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); in xive2_tctx_need_resend()
1022 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); in xive2_tctx_set_cppr()
H A Dspapr_xive_kvm.c420 if (xive_get_field32(END_W0_UCOND_NOTIFY, end->w0)) { in kvmppc_xive_set_queue_config()
430 kvm_eq.qshift = xive_get_field32(END_W0_QSIZE, end->w0) + 12; in kvmppc_xive_set_queue_config()
H A Dxive.c1444 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_queue_pic_print_info()
1476 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_pic_print_info()
1516 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_enqueue()
/qemu/tests/tcg/aarch64/system/
H A Dpauth-3.c30 [w0] "r" (d[2]), in main()
/qemu/crypto/
H A Daes.c1066 uint32_t w0, w1, w2, w3; in aesenc_SB_SR_MC_AK_swap() local
1068 w0 = (AES_Te0[st->b[swap_b ^ AES_SH(0x0)]] ^ in aesenc_SB_SR_MC_AK_swap()
1090 w0 = bswap32(w0); in aesenc_SB_SR_MC_AK_swap()
1096 r->w[swap_w ^ 0] = rk->w[swap_w ^ 0] ^ w0; in aesenc_SB_SR_MC_AK_swap()
1228 uint32_t w0, w1, w2, w3; in aesdec_ISB_ISR_IMC_AK_swap() local
1230 w0 = (AES_Td0[st->b[swap_b ^ AES_ISH(0x0)]] ^ in aesdec_ISB_ISR_IMC_AK_swap()
1252 w0 = bswap32(w0); in aesdec_ISB_ISR_IMC_AK_swap()
1258 r->w[swap_w ^ 0] = rk->w[swap_w ^ 0] ^ w0; in aesdec_ISB_ISR_IMC_AK_swap()
/qemu/include/libdecnumber/
H A DdecNumberLocal.h117 uInt u0, u1, v0, v1, w0, w1, w2, t; \
120 w0=u0*v0; \
121 t=u1*v0 + (w0>>16); \
/qemu/tests/tcg/mips/include/
H A Dwrappers_msa.h38 RESET_MSA_REGISTER(w0); in reset_msa_registers()