| /qemu/target/arm/tcg/ |
| H A D | neon_helper.c | 72 #define NEON_UNPACK(vtype, dest, val) do { \ in NEON_TYPE4() argument
74 vtype v; \ in NEON_TYPE4()
82 #define NEON_PACK(vtype, dest, val) do { \ argument
84 vtype v; \
102 #define NEON_VOP_BODY(vtype, n) \ argument
105 vtype vsrc1; \
106 vtype vsrc2; \
107 vtype vdest; \
108 NEON_UNPACK(vtype, vsrc1, arg1); \
109 NEON_UNPACK(vtype, vsrc2, arg2); \
[all …]
|
| /qemu/linux-headers/asm-riscv/ |
| H A D | ptrace.h | 103 unsigned long vtype; member
117 unsigned long vtype; member
|
| /qemu/target/riscv/tcg/ |
| H A D | tcg-cpu.c | 120 int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); in riscv_get_tb_cpu_state()
121 uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); in riscv_get_tb_cpu_state()
129 FIELD_EX64(env->vtype, VTYPE, VLMUL)); in riscv_get_tb_cpu_state()
132 FIELD_EX64(env->vtype, VTYPE, VTA)); in riscv_get_tb_cpu_state()
134 FIELD_EX64(env->vtype, VTYPE, VMA)); in riscv_get_tb_cpu_state()
|
| /qemu/tcg/riscv/ |
| H A D | tcg-target.c.inc | 537 /* Vector vtype */
546 TCGArg rs1, uint32_t vtype)
548 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (vtype & 0x7ff) << 20;
552 uint32_t uimm, uint32_t vtype)
554 return opc | (rd & 0x1f) << 7 | (uimm & 0x1f) << 15 | (vtype & 0x3ff) << 20;
2986 static bool vtype_check(unsigned vtype)
2990 /* vsetvl tmp, zero, vtype */
2991 asm(".insn r 0x57, 7, 0x40, %0, zero, %1" : "=r"(tmp) : "r"(vtype));
3000 unsigned vtype = encode_vtype(true, true, vsew, lmul & 7);
3016 if (lmul < 0 && (lmul < -3 || !vtype_check(vtype))) {
[all …]
|
| /qemu/target/riscv/ |
| H A D | vector_internals.h | 118 uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); in vext_get_total_elems()
|
| H A D | vcrypto_helper.c | 462 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); in HELPER()
671 uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); in HELPER()
772 uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); in HELPER()
|
| H A D | machine.c | 147 VMSTATE_UINTTL(env.vtype, RISCVCPU),
|
| H A D | cpu.h | 212 target_ulong vtype; member
|
| H A D | vector_helper.c | 70 env->vtype = 0; in HELPER()
87 env->vtype = s2; in HELPER()
5402 uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
|
| H A D | csr.c | 923 *val = (target_ulong)vill | env->vtype; in read_vtype()
|
| /qemu/target/riscv/kvm/ |
| H A D | kvm-cpu.c | 861 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); in kvm_riscv_get_regs_vector()
865 env->vtype = reg; in kvm_riscv_get_regs_vector()
917 reg = env->vtype; in kvm_riscv_put_regs_vector()
918 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); in kvm_riscv_put_regs_vector()
|
| /qemu/tcg/ |
| H A D | tcg.c | 5140 TCGType itype, vtype; in tcg_reg_alloc_dup() local
5153 vtype = TCGOP_TYPE(op); in tcg_reg_alloc_dup()
5191 if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { in tcg_reg_alloc_dup()
5215 if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, in tcg_reg_alloc_dup()
5228 ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); in tcg_reg_alloc_dup()
5957 TCGType vtype = TCGOP_TYPE(op); in tcg_reg_alloc_dup2() local
6002 tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); in tcg_reg_alloc_dup2()
6015 if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, in tcg_reg_alloc_dup2()
|
| /qemu/target/riscv/insn_trans/ |
| H A D | trans_rvv.c.inc | 1487 * load and store whole register instructions ignore vtype and vl setting.
3955 * Whole Vector Register Move Instructions depend on vtype register(vsew).
|