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Searched refs:vs2 (Results 1 – 7 of 7) sorted by relevance

/qemu/target/riscv/
H A Dvector_internals.h144 static void do_##NAME(void *vd, void *vs2, int i) \
146 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
151 void HELPER(NAME)(void *vd, void *v0, void *vs2, \
171 do_##NAME(vd, vs2, i); \
180 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
183 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
186 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
190 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
197 void *vs2, CPURISCVState *env, \
200 do_vext_vv(vd, v0, vs1, vs2, env, desc, \
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H A Dvcrypto_helper.c217 void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
228 round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \
229 round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \
243 void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
254 round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \
255 round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \
306 uint32_t *vs2 = vs2_vptr; local
325 rk[0] = vs2[i * 4 + H4(0)];
326 rk[1] = vs2[i * 4 + H4(1)];
327 rk[2] = vs2[i * 4 + H4(2)];
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H A Dvector_internals.c58 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, in do_vext_vv() argument
77 fn(vd, vs1, vs2, i); in do_vext_vv()
84 void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, in do_vext_vx() argument
103 fn(vd, s1, vs2, i); in do_vext_vx()
H A Dvector_helper.c536 uint32_t idx, void *vs2);
540 uint32_t idx, void *vs2) \
542 return (base + *((ETYPE *)vs2 + H(idx))); \
552 void *vs2, CPURISCVState *env, uint32_t desc, in GEN_VEXT_GET_INDEX_ADDR()
577 abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz); in GEN_VEXT_GET_INDEX_ADDR()
589 void *vs2, CPURISCVState *env, uint32_t desc) \
591 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
614 void *vs2, CPURISCVState *env, uint32_t desc) \ in GEN_VEXT_LD_INDEX()
616 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ in GEN_VEXT_LD_INDEX()
1126 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ in RVVCALL()
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/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc312 static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
317 require_align(vs2, emul) &&
343 * register (vs2) group.
346 * the source vector register (vs2) group for
349 static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
354 bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
362 if (seg_vd != vs2) {
363 ret &= require_noover(seg_vd, s->lmul, vs2, emul);
366 ret &= require_noover(seg_vd, s->lmul, vs2, emul);
371 * the source vector register (vs2) group for
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H A Dtrans_rvvk.c.inc287 static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
290 return !is_overlapped(vd, op_size, vs2, 1);
/qemu/tcg/riscv/
H A Dtcg-target.c.inc522 TCGReg vs2, bool vm)
525 (vs2 & 0x1f) << 20 | (vm << 25);
676 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
680 TCGReg vd, TCGReg vs2, TCGReg vs1)
682 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true));
686 TCGReg vd, TCGReg vs2, TCGReg rs1)
688 tcg_out32(s, encode_v(opc, vd, rs1, vs2, true));
692 TCGReg vd, TCGReg vs2, int32_t imm)
694 tcg_out32(s, encode_vi(opc, vd, imm, vs2, true));
698 TCGReg vd, TCGReg vs2, TCGArg vi1, int c_vi1)
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