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Searched refs:vlenb (Results 1 – 14 of 14) sorted by relevance

/qemu/target/riscv/
H A Dgdbstub.c143 uint16_t vlenb = cpu->cfg.vlenb; in riscv_gdb_get_vector() local
147 for (i = 0; i < vlenb; i += 8) { in riscv_gdb_get_vector()
149 env->vreg[(n * vlenb + i) / 8]); in riscv_gdb_get_vector()
161 uint16_t vlenb = cpu->cfg.vlenb; in riscv_gdb_set_vector() local
164 for (i = 0; i < vlenb; i += 8) { in riscv_gdb_set_vector()
165 env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); in riscv_gdb_set_vector()
167 return vlenb; in riscv_gdb_set_vector()
306 int bitsize = cpu->cfg.vlenb << 3; in ricsv_gen_dynamic_vector_feature()
H A Dvector_internals.h117 uint32_t vlenb = simd_maxsz(desc); in vext_get_total_elems() local
121 return (vlenb << emul) / esz; in vext_get_total_elems()
H A Dcpu_cfg_fields.h.inc161 TYPED_FIELD(uint16_t, vlenb, 0)
H A Dcpu.c628 uint16_t vlenb = cpu->cfg.vlenb; in riscv_cpu_dump_state() local
633 for (j = vlenb - 1 ; j >= 0; j--) { in riscv_cpu_dump_state()
634 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); in riscv_cpu_dump_state()
1115 cpu->cfg.vlenb = 128 >> 3; in riscv_cpu_init()
1684 uint16_t cpu_vlen = cpu->cfg.vlenb << 3; in prop_vlen_set()
1704 cpu->cfg.vlenb = value >> 3; in prop_vlen_set()
1710 uint16_t value = RISCV_CPU(obj)->cfg.vlenb << 3; in prop_vlen_get()
3060 .cfg.vlenb = 256 >> 3,
H A Dcpu.h820 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, in vext_get_vlmax() argument
823 uint32_t vlen = vlenb << 3; in vext_get_vlmax()
H A Dvector_helper.c51 uint16_t vlen = cpu->cfg.vlenb << 3; in HELPER()
78 vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in HELPER()
104 uint32_t vlenb = simd_maxsz(desc); in vext_max_elems() local
108 return scale < 0 ? vlenb >> -scale : vlenb << scale; in vext_max_elems()
813 uint32_t vlenb = riscv_cpu_cfg(env)->vlenb; in GEN_VEXT_LDFF() local
814 uint32_t max_elems = vlenb >> log2_esz; in GEN_VEXT_LDFF()
1203 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
1243 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
1453 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
1520 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
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H A Dcsr.c937 *val = riscv_cpu_cfg(env)->vlenb; in read_vlenb()
992 env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); in write_vstart()
/qemu/util/
H A Dcpuinfo-riscv.c153 unsigned long vlenb; in cpuinfo_init() local
155 asm volatile(".insn i 0x73, 0x2, %0, zero, -990" : "=r"(vlenb)); in cpuinfo_init()
156 assert(vlenb >= 8); in cpuinfo_init()
157 assert(is_power_of_2(vlenb)); in cpuinfo_init()
159 riscv_lg2_vlenb = ctz32(vlenb); in cpuinfo_init()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvbf16.c.inc83 ctx->cfg_ptr->vlenb,
84 ctx->cfg_ptr->vlenb, data,
108 ctx->cfg_ptr->vlenb,
109 ctx->cfg_ptr->vlenb, data,
138 ctx->cfg_ptr->vlenb,
139 ctx->cfg_ptr->vlenb, data,
H A Dtrans_rvvk.c.inc175 s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
265 simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); \
340 simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); \
405 s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
455 vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
456 s->cfg_ptr->vlenb, data,
486 vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
487 s->cfg_ptr->vlenb, data,
H A Dtrans_rvv.c.inc257 return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlenb;
703 * The first part is vlen in bytes (vlenb), encoded in maxsz of simd_desc.
706 desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
707 s->cfg_ptr->vlenb, data));
873 int max_sz = s->cfg_ptr->vlenb << 3;
1219 desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
1220 s->cfg_ptr->vlenb, data));
1355 desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
1356 s->cfg_ptr->vlenb, data));
1422 uint32_t size = s->cfg_ptr->vlenb * nf;
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/qemu/linux-headers/asm-riscv/
H A Dptrace.h105 unsigned long vlenb; member
119 unsigned long vlenb; member
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c89 size_b = cpu->cfg.vlenb; in kvm_riscv_vector_reg_id()
443 .offset = CPU_CFG_OFFSET(vlenb),
445 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
868 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), &reg); in kvm_riscv_get_regs_vector()
872 cpu->cfg.vlenb = reg; in kvm_riscv_get_regs_vector()
924 reg = cpu->cfg.vlenb; in kvm_riscv_put_regs_vector()
925 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), &reg); in kvm_riscv_put_regs_vector()
1185 cpu->cfg.vlenb = val; in kvm_riscv_read_vlenb()
2063 if (cpu->cfg.vlenb != val) { in riscv_kvm_cpu_finalize_features()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in riscv_get_tb_cpu_state()
419 uint32_t vlen = cfg->vlenb << 3; in riscv_cpu_validate_v()