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Searched refs:virt_enabled (Results 1 – 12 of 12) sorted by relevance

/qemu/target/riscv/
H A Dop_helper.c152 if (env->virt_enabled && in check_zicbo_envcfg()
275 target_ulong prev_priv, prev_virt = env->virt_enabled; in helper_sret()
277 const bool src_virt = env->virt_enabled; in helper_sret()
294 if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { in helper_sret()
310 if (!env->virt_enabled && prev_vu) { in helper_sret()
324 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret()
492 env->priv, env->virt_enabled); in helper_ctr_add_entry()
516 uint32_t excep = env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : in helper_ctr_clear()
532 (rvs && prv_u && !env->virt_enabled)) { in helper_wfi()
534 } else if (env->virt_enabled && in helper_wfi()
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H A Dcpu_helper.c45 bool virt = env->virt_enabled; in riscv_env_mmu_index()
84 if (env->virt_enabled) { in cpu_get_fcfien()
113 if (env->virt_enabled) { in cpu_get_bcfien()
488 if (env->virt_enabled) { in riscv_cpu_local_irq_pending()
568 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { in riscv_cpu_fp_enabled()
581 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { in riscv_cpu_vector_enabled()
599 bool current_virt = env->virt_enabled; in riscv_cpu_swap_hypervisor_regs()
729 if (env->virt_enabled) { in riscv_cpu_interrupt()
857 } else if (env->virt_enabled && tgt_prv == PRV_S) { in riscv_ctr_check_xte()
935 bool tgt_virt = env->virt_enabled; in riscv_ctr_add_entry()
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H A Dpmu.c109 bool virt_on = env->virt_enabled; in riscv_pmu_incr_ctr_rv32()
150 bool virt_on = env->virt_enabled; in riscv_pmu_incr_ctr_rv64()
206 if (env->virt_enabled) { in riscv_pmu_icount_update_priv()
246 if (env->virt_enabled) { in riscv_pmu_cycle_update_priv()
H A Dcsr.c52 bool virt = env->virt_enabled; in smstateen_acc_ok()
150 if (env->virt_enabled) { in ctr()
398 if (env->virt_enabled) { in scountinhibit_pred()
538 bool virt = env->virt_enabled; in sstateen()
603 if (env->virt_enabled) { in sstc()
624 if (env->priv == PRV_S && !env->virt_enabled && in satp()
628 if (env->priv == PRV_S && env->virt_enabled && in satp()
638 if (env->priv == PRV_S && !env->virt_enabled && in hgatp()
681 env->virt_enabled) { in ctr_smode()
814 } else if (env->virt_enabled) { in seed()
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H A Dgdbstub.c217 target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0; in riscv_gdb_get_virtual()
243 if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) { in riscv_gdb_set_virtual()
H A Ddebug.c317 if (env->virt_enabled) { in trigger_priv_match()
326 if (env->virt_enabled) { in trigger_priv_match()
339 if (env->virt_enabled) { in trigger_priv_match()
688 if (env->virt_enabled) { in check_itrigger_priv()
H A Dtranslate.c80 bool virt_enabled; member
686 if (ctx->virt_enabled) { in mark_fs_dirty()
715 if (ctx->virt_enabled) { in mark_vs_dirty()
1267 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); in riscv_tr_init_disas_context()
H A Dmachine.c425 VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
H A Dcpu.h262 bool virt_enabled; member
H A Dcpu.c525 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); in riscv_cpu_dump_state()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvf.c.inc23 ctx->virt_inst_excp = ctx->virt_enabled && ctx->cfg_ptr->ext_zfinx; \
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c164 if (env->virt_enabled) { in riscv_get_tb_cpu_state()