Home
last modified time | relevance | path

Searched refs:vext_ver (Results 1 – 4 of 4) sorted by relevance

/qemu/target/riscv/
H A Dmachine.c419 VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
H A Dcpu.h230 target_ulong vext_ver; member
H A Dcpu.c1120 cpu->env.vext_ver = VEXT_VERSION_1_00_0; in riscv_cpu_init()
1134 cpu->env.vext_ver = mcc->def->vext_spec; in riscv_cpu_init()
1661 cpu->env.vext_ver = VEXT_VERSION_1_00_0; in prop_vext_spec_set()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1595 env->vext_ver = VEXT_VERSION_1_00_0; in riscv_init_max_cpu_extensions()