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Searched refs:trigger_cur (Results 1 – 4 of 4) sorted by relevance

/qemu/target/riscv/
H A Ddebug.c158 int trigger_type = get_trigger_type(env, env->trigger_cur); in tdata_available()
169 return env->trigger_cur; in tselect_csr_read()
175 env->trigger_cur = val; in tselect_csr_write()
853 int count = itrigger_get_count(env, env->trigger_cur), executed; in itrigger_get_adjust_count()
854 if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) { in itrigger_get_adjust_count()
867 env->tdata1[env->trigger_cur]); in tdata_csr_read()
869 return deposit64(env->tdata1[env->trigger_cur], 10, 14, in tdata_csr_read()
872 return env->tdata1[env->trigger_cur]; in tdata_csr_read()
874 return env->tdata2[env->trigger_cur]; in tdata_csr_read()
876 return env->tdata3[env->trigger_cur]; in tdata_csr_read()
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H A Dmachine.c245 VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
H A Dcpu.h435 target_ulong trigger_cur; member
H A Dcsr.c5290 if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { in read_tdata()