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Searched refs:tlbe (Results 1 – 12 of 12) sorted by relevance

/qemu/hw/arm/
H A Dsmmu-common.c459 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) in smmu_ptw_64_s1() argument
555 tlbe->entry.translated_addr = gpa; in smmu_ptw_64_s1()
556 tlbe->entry.iova = iova & ~mask; in smmu_ptw_64_s1()
557 tlbe->entry.addr_mask = mask; in smmu_ptw_64_s1()
558 tlbe->parent_perm = PTE_AP_TO_PERM(ap); in smmu_ptw_64_s1()
559 tlbe->entry.perm = tlbe->parent_perm; in smmu_ptw_64_s1()
560 tlbe->level = level; in smmu_ptw_64_s1()
561 tlbe->granule = granule_sz; in smmu_ptw_64_s1()
568 tlbe->entry.perm = IOMMU_NONE; in smmu_ptw_64_s1()
588 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) in smmu_ptw_64_s2() argument
[all …]
/qemu/hw/ppc/
H A Dppc440_bamboo.c124 booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1U << 31); in main_cpu_reset()
125 booke_set_tlb(&env->tlb.tlbe[1], 0x80000000, 0x80000000, 1U << 31); in main_cpu_reset()
H A Dsam460ex.c236 booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1 << 31); in main_cpu_reset()
243 booke_set_tlb(&env->tlb.tlbe[0], 0xf0000000, 0xf0000000, 0x10000000); in main_cpu_reset()
244 env->tlb.tlbe[0].RPN |= 4; in main_cpu_reset()
H A Dvirtex_ml507.c120 booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1U << 31); in main_cpu_reset()
121 booke_set_tlb(&env->tlb.tlbe[1], 0x80000000, 0x80000000, 1U << 31); in main_cpu_reset()
/qemu/target/ppc/
H A Dmmu_helper.c118 tlb = &env->tlb.tlbe[i]; in ppc4xx_tlb_invalidate_all()
692 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbre_hi()
712 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbre_lo()
751 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbwe_hi()
802 tlb = &env->tlb.tlbe[entry]; in helper_4xx_tlbwe_lo()
862 tlb = &env->tlb.tlbe[entry]; in helper_440_tlbwe()
923 tlb = &env->tlb.tlbe[entry]; in helper_440_tlbre()
H A Dmmu-booke.c63 tlb = &env->tlb.tlbe[i]; in ppcemb_tlb_search()
81 tlb = &env->tlb.tlbe[i]; in mmu40x_get_physical_address()
196 tlb = &env->tlb.tlbe[i]; in mmubooke_get_physical_address()
H A Dmachine.c568 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
H A Dmmu_common.c368 entry = &env->tlb.tlbe[0]; in mmubooke_dump_mmu()
H A Dcpu.h383 ppcemb_tlb_t *tlbe; member
H A Dcpu_init.c6898 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); in init_ppc_proc()
/qemu/accel/tcg/
H A Dcputlb.c1582 CPUTLBEntry *tlbe = tlb_entry(cpu, mmu_idx, addr); in tlb_plugin_lookup() local
1585 uint64_t tlb_addr = tlb_read_idx(tlbe, access_type); in tlb_plugin_lookup()
1816 CPUTLBEntry *tlbe; in atomic_mmu_lookup() local
1828 tlbe = tlb_entry(cpu, mmu_idx, addr); in atomic_mmu_lookup()
1831 tlb_addr = tlb_addr_write(tlbe); in atomic_mmu_lookup()
1839 tlbe = tlb_entry(cpu, mmu_idx, addr); in atomic_mmu_lookup()
1841 tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; in atomic_mmu_lookup()
1850 if (unlikely(tlbe->addr_read == -1)) { in atomic_mmu_lookup()
1879 tlb_addr |= tlbe->addr_read; in atomic_mmu_lookup()
1891 hostaddr = (void *)((uintptr_t)addr + tlbe->addend); in atomic_mmu_lookup()
/qemu/include/hw/arm/
H A Dsmmu-common.h193 IOMMUAccessFlags perm, SMMUTLBEntry *tlbe,