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Searched refs:tdata2 (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Ddebug.c478 target_ulong addr = env->tdata2[index]; in type2_breakpoint_insert()
543 if (val != env->tdata2[index]) { in type2_reg_write()
544 env->tdata2[index] = val; in type2_reg_write()
603 target_ulong addr = env->tdata2[index]; in type6_breakpoint_insert()
657 if (val != env->tdata2[index]) { in type6_reg_write()
658 env->tdata2[index] = val; in type6_reg_write()
874 return env->tdata2[env->trigger_cur]; in tdata_csr_read()
962 pc = env->tdata2[i]; in riscv_cpu_debug_check_breakpoint()
971 pc = env->tdata2[i]; in riscv_cpu_debug_check_breakpoint()
1008 addr = env->tdata2[i]; in riscv_cpu_debug_check_watchpoint()
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H A Dmachine.c247 VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
H A Dcpu.h437 target_ulong tdata2[RV_MAX_TRIGGERS]; member